Passivation Pattern Structure for Scaled MOSFET Isolation Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate due to size reduction, leading to reliability and electrical characteristic issues.
Innovation Solution
A semiconductor device design featuring a stacked channel pattern with passivation patterns between the device isolation layer and active pattern sidewalls, along with a gate dielectric layer covering the passivation patterns, is implemented. This design includes a method of fabricating the device by alternately stacking sacrificial and active layers, forming trenches, and replacing sacrificial layers with a gate electrode, while using passivation layers to maintain structural integrity and prevent excessive recessing of the device isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFET sizes are scaled down to increase integration density, then device miniaturization is achieved, but operating characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from planar channel structures to vertically stacked channel patterns (multi-layer channel structures). This dimensional change allows multiple channels to occupy the same footprint area, increasing effective channel width without lateral scaling, thereby maintaining electrical characteristics while achieving device miniaturization through vertical integration
Solution Approach 2:
The channel region is divided into multiple discrete stacked channels separated by channel isolation layers. This segmentation allows independent formation and control of each channel layer, enabling precise thickness control and electrical characteristics optimization for each channel while maintaining compact overall device structure
2Ease of manufacture
If device isolation layer is formed to define active patterns, then device separation is achieved, but excessive recessing occurs leading to structural instability
Solution Approach 1:
Passivation layers are formed on the sidewalls of active patterns before device isolation layer formation. This preliminary action provides structural support and prevents excessive recessing of the isolation layer during subsequent processing steps, ensuring structural stability while maintaining ease of manufacture
Solution Approach 2:
The passivation layer acts as an intermediary structure between the active pattern sidewalls and the device isolation layer. It provides mechanical support to prevent isolation layer collapse or excessive recessing, while also serving as a barrier layer for process control and structural definition
3Stability of the object's composition
If gate dielectric layer covers passivation patterns, then structural integrity is maintained, but manufacturing complexity increases
Solution Approach 1:
The gate dielectric layer formation process serves multiple functions: it provides electrical isolation between gate and channel, covers and protects passivation patterns, and establishes the foundation for gate electrode formation. This multi-functionality maintains structural integrity while avoiding additional dedicated process steps that would increase manufacturing complexity
Data Source
AI summary
A semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench that defines the first active pattern, a first channel pattern and a first source/drain pattern disposed on the first active pattern in which the first channel pattern includes semiconductor patterns stacked and spaced apart from each other, a gate electrode that extends and runs across the first channel pattern, a gate dielectric layer disposed between the first channel pattern and the gate electrode, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper part that protrudes upwardly from the device isolation layer, and a lower part buried in the device isolation layer. The gate dielectric layer covers the upper part of the first passivation pattern.