Semiconductor Passivation Layer Seam Prevention via Corner Extraction
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Solution Overview
Problem
Conventional passivation layers in semiconductor devices often form seams at the bottom side-wall corners, leading to cracking during the wet etching process, which compromises the integrity of the layer.
Innovation Solution
A semiconductor device and manufacturing method that utilize a dielectric layer, a poly-silicon etch-stop layer, and a passivation layer with an opening to expose the connection pad and transition region, allowing for the removal of passivation layer portions at the bottom side-wall corners to prevent seams and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional passivation layer is deposited to cover features, then the features are protected, but seams form at the bottom side-wall corners causing cracking during wet etching
Solution Approach 1:
The patent removes the problematic bottom side-wall corners of features before depositing the passivation layer. By extracting these corners through selective etching, the passivation layer can be deposited conformally without forming seams at the corners, thereby eliminating the source of cracking while maintaining protective coverage.
Solution Approach 2:
The patent performs preliminary corner removal of features before depositing the passivation layer. This preliminary action modifies the feature geometry in advance to prevent seam formation during subsequent passivation layer deposition, ensuring a defect-free layer without requiring post-deposition repair.
2Manufacturing precision
If the passivation layer is made continuous and conformal, then coverage is improved, but seams still form at bottom side-wall corners
Solution Approach 1:
The patent extracts the bottom side-wall corners of features through selective etching before passivation layer deposition. This removal of corner material eliminates the geometric discontinuity that causes seam formation, allowing the passivation layer to be deposited as a continuous, conformal film without defects.
Solution Approach 2:
The patent applies local quality modification by selectively removing only the bottom side-wall corners of features while leaving the rest of the feature structure intact. This localized geometric modification enables conformal passivation layer deposition without compromising the overall feature coverage or requiring global structure changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a seam-free passivation layer, enhancing the reliability and integrity of the semiconductor device by preventing cracking during the wet etching process.
Implementation Method 1
a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer
Data Source
AI summary
Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.