Passivation Layer Layout for Thermal Stress Crack Reduction
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Solution Overview
Problem
The mismatch in coefficients of thermal expansion (CTE) between dielectric and metal features in semiconductor devices leads to stress that can cause the passivation layer to peel or crack, resulting in device failures and reduced lifetime.
Innovation Solution
Incorporating a top metal feature or dummy metal feature partially below the space between adjacent redistribution features to reduce stress on the passivation layer, with configurations such as aligning edges of top metal features with redistribution features and inserting dummy metal features to mitigate tensile stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric passivation layer is disposed over metal redistribution features, then insulation is provided, but CTE mismatch causes stress leading to peeling and cracks
Solution Approach 1:
A buffer layer is introduced between the metal redistribution feature and the dielectric passivation layer. This buffer layer acts as an intermediary that absorbs and distributes the thermal stress generated by CTE mismatch, preventing direct stress transfer to the passivation layer and thereby reducing peeling and cracking while maintaining insulation functionality.
2Adaptability or versatility
If metal redistribution layer shrinks more than passivation layer during cooling, then CTE mismatch is demonstrated, but this results in peeling or cracks in passivation layer
Solution Approach 1:
The buffer layer is designed with specific material parameters including intermediate CTE value between metal and dielectric, controlled thickness, and adjusted mechanical properties. By optimizing these parameters, the buffer layer adapts to thermal contraction during cooling, distributing stress to maintain passivation layer bonding strength while accommodating the inherent CTE mismatch between metal and dielectric materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces tensile stress on the passivation layer by up to 40%, minimizing delamination and crack formation, thereby enhancing the reliability and longevity of semiconductor devices.
Implementation Method 1
When a workpiece is cooling down from an elevated temperature for deposition of the passivation layer, the metal redistribution layer may shrink more in volume than the neighboring passivation layer
Implementation Method 2
Incorporating a top metal feature or dummy metal feature partially below the space between adjacent redistribution features to reduce stress on the passivation layer
Data Source
AI summary
Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.