Group III-V Passivation with Alternating Stress Dielectric Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Group III-V semiconductor devices with thick plated gold conductors face manufacturing challenges due to stress mismatches between the interlayer dielectric, gold conductors, and passivation layers, leading to compromised hermeticity and reliability when exposed to moisture.
Innovation Solution
The semiconductor device incorporates a passivation layer with stacked regions of dielectric material under alternating tensile and compressive stress, which compensates for the thermal expansion differences and enhances mechanical integrity, preventing cracks and maintaining hermeticity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick layer of gold is deposited by plating as the conductor material to minimize resistance, then the electrical conductivity is improved, but stress mismatches between the gold conductors, interlayer dielectric layer, and passivation layer worsen
Solution Approach 1:
The passivation layer is divided into multiple sub-layers with different stress characteristics. This segmentation allows each sub-layer to compensate for stress mismatches differently, preventing crack formation while maintaining the thick gold conductor structure for low resistance.
Solution Approach 2:
The invention changes the stress parameters of the passivation layer by using multiple sub-layers with different deposition conditions. This allows optimization of stress distribution to match the thermal expansion coefficients of the gold conductor and interlayer dielectric, resolving the stress mismatch problem.
2Reliability
If a thick passivation layer is used to improve moisture resistance, then hermeticity is improved, but cracks form at the corners where the passivation layer follows contour changes from conductors, worsening reliability
Solution Approach 1:
The thick passivation layer is segmented into multiple sub-layers. This segmentation distributes the mechanical stress across layers rather than concentrating it in a single thick layer, preventing crack formation at contour changes while maintaining overall hermeticity.
Solution Approach 2:
The multi-layer structure acts as a cushioning mechanism that absorbs and distributes stress before it can concentrate and cause cracks. Each sub-layer provides a buffer zone that prevents stress propagation to critical corners.
3Object-affected harmful factors
If the passivation layer is made thick to prevent moisture penetration, then moisture resistance is improved, but the stress mismatch with the interlayer dielectric and gold conductors worsens
Solution Approach 1:
The thick passivation layer is divided into multiple sub-layers, each contributing to moisture barrier function while distributing stress. This maintains the thickness needed for moisture resistance while eliminating the stress concentration that would occur in a single thick layer.
Solution Approach 2:
The passivation structure uses a composite multi-layer design where each layer has optimized properties. This composite structure provides both the thickness needed for moisture protection and the stress distribution needed to prevent cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves the hermeticity and reliability of the semiconductor device by reducing the likelihood of cracks in the passivation layer, as demonstrated by resistance to moisture penetration and prolonged temperature/humidity bias life stress tests.
Implementation Method 1
The passivation layer includes stacked regions of dielectric material under alternating tensile and compressive stress that compensate for the thermal expansion differences
Implementation Method 2
typically deposited by a plating process, as the material of the conductors
Data Source
AI summary
A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.