Semiconductor Passivation Testing for Early 3DIC Yield Screening

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Solution Overview

Problem

The integration of 3DICs faces challenges related to detecting malfunctioning semiconductor structures early in the manufacturing process, leading to reduced yield and increased costs.

Innovation Solution

Conducting multiple electrical tests at different stages of the semiconductor structure manufacturing process, including the formation of a first and second passivation layer with electrical probes, and using a carrier substrate with bonding layers to enhance structural strength and attachment, thereby facilitating early detection of malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple electrical tests are conducted at different stages of manufacturing, then malfunction detection capability is improved and yield is increased, but process complexity and manufacturing time are increased

Engineering Contradiction:
ImproveyieldVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary electrical testing at multiple stages during the manufacturing process, specifically after forming the first passivation layer and after forming the second passivation layer. This allows malfunctions to be detected early before completing the entire manufacturing process, enabling defective structures to be identified and removed from further processing, thereby increasing overall yield while managing process complexity through staged testing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple electrical tests are conducted at different stages of manufacturing, then malfunction detection capability is improved, but manufacturing time is increased

Engineering Contradiction:
Improvemalfunction detection capabilityVSAvoidmanufacturing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary electrical tests at intermediate stages during manufacturing rather than only after completion. By testing after the first passivation layer is formed and again after the second passivation layer is formed, the process identifies defective structures early, allowing them to be excluded from subsequent time-consuming manufacturing steps, thereby reducing total manufacturing time despite adding test steps.

Inventive Principle:
Principle #10Preliminary action

3Strength

If carrier substrate with bonding layers is used to enhance structural strength, then attachment between passivation layers and oxide materials is improved, but device complexity is increased

Engineering Contradiction:
Improvestructural integrityVSAvoiddevice complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent introduces a carrier substrate with bonding layers as an intermediary component between the passivation layers and oxide materials. The bonding layers serve as mediators that enhance the attachment and structural integrity of the semiconductor structure. While this adds device complexity, it provides necessary mechanical support and improves reliability during manufacturing and operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250266300A1Method for forming semiconductor structure
Publication Date: 2025.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250266300A1 patent drawing
  • US20250266300A1 patent drawing
  • US20250266300A1 patent drawing

AI summary

A method for forming a semiconductor structure is provided. The method includes forming a first passivation layer over an interconnect structure. The first passivation exposes a conductive feature electrically connected to the interconnect structure. The method includes performing an electrical test on the conductive feature. The method includes covering the conductive feature using an oxide material. The method also includes attaching a carrier substrate over the oxide material using a bonding layer.