Passive Adder Quantizer Circuit for Low-Power Signal Summing
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Solution Overview
Problem
Existing analog-to-digital converters for summing signals face power and area consumption challenges due to conflicting requirements between adder and quantizer in feed-forward sigma-delta modulators, particularly in multi-bit implementations where multiple comparators and amplifiers are needed, leading to high power and area overhead.
Innovation Solution
A circuit that uses a passive adder for summing multiple input signals and a single comparator for quantization, reducing power consumption by eliminating the need for multiple comparators and amplifiers, while maintaining efficient digitization through a multi-bit quantizer and control logic block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparators and amplifiers are used in multi-bit flash quantizers for signal summation, then quantization resolution is improved, but power consumption and area increase exponentially
Solution Approach 1:
The patent segments the quantization process into multiple single-bit quantization stages instead of using a single multi-bit flash quantizer. Each stage processes a portion of the signal sum, and the results are combined digitally. This segmentation reduces the number of comparators from exponential (2^N-1 for N-bit flash) to linear scaling with resolution, directly addressing the power consumption issue while maintaining quantization accuracy.
Solution Approach 2:
The patent transitions from a spatial approach (multiple parallel comparators in flash quantizer) to a temporal approach (sequential single-bit quantization stages). By moving the quantization process across time dimensions rather than using all comparators simultaneously in space, the patent achieves high resolution without the exponential power penalty of parallel flash architecture.
2Measurement precision
If multiple amplifiers are used in active adders for signal summation, then signal dynamic range is maintained, but power consumption increases
Solution Approach 1:
The patent replaces the active amplifier-based addition mechanism with a passive resistor-based voltage summation approach. Instead of using multiple power-consuming amplifiers to maintain signal dynamic range, the patent uses resistive networks to passively sum voltages, achieving the same signal combination function with significantly reduced power consumption while maintaining adequate signal levels for subsequent quantization stages.
3Use of energy by stationary object
If a single comparator is used for quantization, then power consumption is reduced, but quantization resolution may be compromised
Solution Approach 1:
The patent segments the high-resolution quantization task into multiple single-bit quantization stages. Each stage uses a simple single-bit comparator, but the cumulative effect of multiple stages achieves the desired high resolution. This segmentation allows the use of low-power single-bit comparators while maintaining overall system resolution through digital combination of stage outputs.
Solution Approach 2:
The patent introduces digital processing elements as intermediaries between the single-bit quantization stages. These digital components combine the results from multiple single-bit stages to reconstruct the high-resolution signal, acting as mediators that bridge the gap between simple single-bit comparators and the need for high overall quantization resolution.
Data Source
AI summary
A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.