Passive Charge Sharing Circuitry for Analog Signal Processing
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Solution Overview
Problem
Existing discrete time analog signal processing modules face challenges in reducing power consumption and circuit area, particularly in implementing scalable and efficient signal processing without active devices in the signal path.
Innovation Solution
The use of passive charge sharing circuitry with reconfigurable multiplicative scaling stages, where digital multiplicative coefficients are transformed to configure capacitive elements for achieving a linear relationship between desired coefficients and charge transfer, allowing for higher resolution with smaller capacitor arrays and multiple successive charge sharing phases to achieve a large dynamic range of coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional linear Capacitive Digital to Analog Converter (CapDAC) implementations are used, then circuit area is increased, but resolution is improved
Solution Approach 1:
The patent segments the capacitor array into multiple smaller capacitor arrays, each handling a portion of the resolution requirement. This segmentation allows the system to achieve high resolution through multiple successive charge sharing phases rather than requiring a single large high-resolution capacitor array, thereby reducing overall circuit area while maintaining resolution.
Solution Approach 2:
The patent employs multiple successive charge sharing phases to progressively build up the resolution. Each phase contributes to the final resolution through periodic charge transfer operations, allowing the system to achieve high resolution over time rather than requiring all capacitors to be present simultaneously, thus reducing circuit area.
2Productivity
If active elements are used for combining analog signals, then signal processing capability is improved, but power consumption is increased
Solution Approach 1:
The patent extracts and eliminates active elements from the signal path by using passive charge sharing circuitry to perform signal combination and scaling functions. This extraction of active elements directly reduces power consumption while maintaining signal processing capability through clever use of capacitive charge transfer and sharing mechanisms.
Solution Approach 2:
The passive charge sharing circuitry performs signal processing functions autonomously without requiring external active elements. The capacitors and switches in the circuit self-organize to perform scaling and combination operations through charge sharing, eliminating the need for additional active devices that would consume power.
3Adaptability or versatility
If a large dynamic range of coefficients is achieved, then signal processing flexibility is improved, but circuit complexity is increased
Solution Approach 1:
The patent implements dynamic reconfiguration capability where the capacitor arrays can be programmatically adjusted during operation to achieve different scaling factors and coefficient values. This dynamic reconfiguration allows a wide range of coefficients to be achieved using the same physical hardware, avoiding the need for multiple fixed circuits and thereby reducing overall complexity.
Solution Approach 2:
The patent creates a universal charge sharing circuit structure that can perform multiple signal processing functions with different coefficient values. The same capacitor arrays and charge sharing mechanism serve multiple purposes by being reconfigured through digital control, eliminating the need for separate dedicated circuits for each function and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and circuit area while providing a large dynamic range of coefficients, improving signal-to-noise characteristics and enabling greater precision in scaling factors, and allows for flexible configuration of filters and processing modes.
Implementation Method 1
a signal value is presented, for example, at an input or after an intermediate active buffer, in voltage form, and can be converted to a charge representation by coupling the voltage to a capacitor
Implementation Method 2
In phase 2, the capacitors 120 are coupled together through switches 130 that are closed forming a parallel combination of capacitors 120 with a total capacitance of The total charge on the capacitors, is therefore shared among all the coupled capacitors, resulting in an equilibration of the voltages across the capacitors
Data Source
Figure 1A~1B
Figure 2~3B
Figure 4
AI summary
In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements.; The scaling circuits can be combined to form configurable time domain or frequency domain filters.