Passive Multi-Input Comparator for ODVS Common-Mode Rejection
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Solution Overview
Problem
Existing Multi-Input Comparator (MIC) embodiments that rely on active input elements face issues with signal dynamic range and common mode rejection, particularly in Orthogonal Differential Vector Signaling (ODVS) codes like ENRZ, where modulation of one subchannel can present as a varying common mode offset in other subchannels.
Innovation Solution
A passive MIC embodiment using an interconnected resistor network to sum input terms before active detection, reducing detrimental effects of common mode signal variation and increasing dynamic range, by generating combinations of symbols on output nodes and utilizing differential transistor pairs for sub-channel outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If active input elements are used in Multi-Input Comparator (MIC) embodiments, then active detection of subchannel results can be achieved, but signal dynamic range is reduced and common mode rejection is worsened
Solution Approach 1:
The patent introduces passive resistor networks as intermediary elements between the multi-wire bus inputs and the active differential transistor pairs. These resistor networks serve as mediators that passively sum the input signals before they reach the active detection stage, thereby isolating the active elements from direct exposure to common mode variations while preserving detection precision
Solution Approach 2:
The patent replaces active input elements with passive resistor network summation. By substituting active components with passive resistive elements for the signal combining function, the system eliminates the harmful interaction between active input stages and common mode signal variations, while maintaining the necessary detection capability through subsequent differential transistor pairs
2Productivity
If conventional differential signaling is used, then signal transmission can be achieved, but dynamic range is limited due to common mode offset variations
Solution Approach 1:
The patent segments the signal processing function into two distinct stages: a passive resistor network stage that performs signal summation without active amplification, and a subsequent active differential transistor pair stage that performs precise detection. This segmentation allows the first stage to handle common mode variations passively while the second stage operates with optimized dynamic range for detection
Solution Approach 2:
The patent performs preliminary signal summation using passive resistor networks before the signals reach the active differential detection stage. By pre-combining the input signals from the multi-wire bus in a passive manner, the system prepares the signals for optimal detection while avoiding the introduction of common mode offsets that would occur if active elements were used at the input stage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passive approach enhances the dynamic range and reduces common mode rejection issues, improving the detection of ODVS codes by passively combining wire signals before conventional differential signal reception, leading to more robust and efficient sub-channel output generation.
Implementation Method 1
passive resistor networks are used to sum at least some of the input terms of that code before active detection
Implementation Method 2
generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes
Data Source
AI summary
Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.