Passive Device Module Embedded in Semiconductor Package

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Fan-out panel level packaging (FO-PLP) semiconductor packages face challenges in reducing thickness due to the presence of passive devices like coils and capacitors, which increase the package thickness and limit the placement of lower bumps, making it difficult to secure a sufficient number of passive devices and in/out terminals.

Innovation Solution

The semiconductor package design includes a lower redistribution layer with wiring patterns, a cavity in the lower substrate, an application processor, a cache memory chip, and a passive device module with through-silicon vias connecting the components, allowing the passive device module to be embedded and reducing overall package thickness while maintaining electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If passive devices (coils and capacitors) are placed in the vicinity of bottom lower bumps, then the number of passive devices can be secured, but the package thickness increases

Engineering Contradiction:

Improvenumber of passive devicesVSAvoidpackage thickness

Core Design Contradiction:

Quantity of substanceVSLength of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Passive devices are positioned on the top surface of the application processor rather than at the bottom, allowing vertical stacking with the cache memory chip and application processor. This dimensional change enables securing sufficient passive devices while reducing the horizontal footprint and overall package thickness.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested stacking architecture where the passive device module is positioned on the application processor, which itself is stacked on the lower substrate. The cache memory chip is stacked on the application processor as well, creating a multi-layer nested structure. This nesting allows multiple components to occupy vertical space efficiently, reducing the need for horizontal expansion and minimizing package thickness.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If bottom lower bumps are formed to have a height greater than the thickness of each passive device, then electrical connectivity is improved, but the package thickness increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidpackage thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent extracts the passive devices from the bottom region and relocates them to the top surface of the application processor. This separation allows the lower bumps to be optimized for their intended function without needing excessive height to accommodate passive devices, thereby reducing overall package thickness while maintaining electrical connectivity through the stacked architecture.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent moves passive devices from the horizontal plane at the bottom to the vertical stacking arrangement at the top. This dimensional transition allows electrical connectivity to be achieved through vertical interconnections (via holes and bumps) rather than relying on increased bump height, thus maintaining reliability while reducing thickness.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If the area of the semiconductor package is increased to secure sufficient passive devices and in/out terminals, then device placement is improved, but the package size increases

Engineering Contradiction:

Improvedevice placement flexibilityVSAvoidpackage area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension by implementing a stacked architecture where the application processor, cache memory chip, and passive device module are arranged in multiple layers. This three-dimensional configuration allows sufficient device placement flexibility without increasing the horizontal package area, as components are distributed across vertical levels rather than spread out in a single plane.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges multiple functional components into a compact stacked structure. The passive device module is integrated on the application processor, which is itself stacked on the lower substrate. This merging of functions into a vertical stack maximizes device placement flexibility within a minimized package footprint.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11239219B2Passive device module and semiconductor package including the same

Publication Date: 2022.02.01 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package including a lower redistribution layer including wiring patterns; a lower substrate on the lower redistribution layer, the lower substrate including a cavity; an application processor on the lower redistribution layer in the cavity; a cache memory chip on the application processor; a passive device module on the application processor; a plurality of first through-silicon vias penetrating the application processor to connect the lower redistribution layer to the passive device module; and lower bumps on a bottom surface of the lower redistribution layer, wherein the passive device module is adjacent to a side of the cache memory chip.