Integrated Passive Die Layout for Flexible Sizing and Alignment
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Solution Overview
Problem
Existing integrated passive device dies have fixed sizes and electrical properties, limiting circuit design flexibility and integration possibilities.
Innovation Solution
The development of integrated passive device dies with user-selectable sizes and configurations, achieved by forming a plurality of passive devices on a semiconductor wafer and dicing it along user-defined scribe lines, incorporating seal rings and alignment marks for precise positioning and protection during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed-size integrated passive device dies are used, then manufacturing simplicity is maintained, but design flexibility and integration capabilities are limited
Solution Approach 1:
The patent divides the semiconductor wafer into multiple individual dies, each containing a subset of the total passive devices. Users can select different die sizes and configurations by choosing how many passive devices to include in each die, enabling flexible integration while maintaining standardized manufacturing processes.
Solution Approach 2:
The patent enables dynamic selection of die configurations after wafer fabrication. By defining scribe lines and grouping passive devices into different dies based on user requirements, the system adapts to various integration scenarios without requiring multiple fixed manufacturing processes.
2Productivity
If multiple passive devices are integrated into single dies, then integration density improves, but alignment precision during stacking becomes more challenging
Solution Approach 1:
The patent incorporates alignment marks directly into the passive device structures during wafer fabrication, before dicing and stacking operations. These pre-formed alignment marks serve as reference features for subsequent alignment processes, enabling precise stacking of multiple dies without requiring additional alignment infrastructure.
Solution Approach 2:
The patent creates a common reference plane and alignment marker system across all dies on the wafer. By establishing equipotential alignment references that extend across the entire wafer surface, the system ensures consistent alignment precision regardless of die size or position, facilitating accurate stacking of multiple passive device dies.
Data Source
AI summary
An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material. Embodiments include methods of fabricating the integrated passive dies.