Semiconductor Package Dam Layout for Passive Element Load Relief

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving improved electrical characteristics and reliability, particularly in the integration of passive elements, where the load from these elements can cause connection terminal deformation and void formation due to uneven distribution of stress.

Innovation Solution

Incorporating a dam structure within the upper insulating layer of the semiconductor package, which is equal in thickness to the connection terminal, to support the passive element and maintain even spacing, thereby reducing the load on the connection terminal and preventing voids and delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If passive elements are integrated into the semiconductor package, then functionality is improved, but connection terminal deformation occurs due to load-induced stress

Engineering Contradiction:
ImprovefunctionalityVSAvoidconnection terminal deformation
Core Design Contradiction:
Adaptability or versatilityVSStrength

Solution Approach 1:

The upper insulating layer is segmented into multiple functional regions: a dam region surrounding the passive element, an insulating structure region spaced apart from the passive element, and an exposed base portion region. This segmentation allows each region to independently manage stress distribution, preventing connection terminal deformation while maintaining package functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dam structure acts as an intermediary element between the passive element and the connection terminal. By positioning the dam between these components, it mediates the stress transmission, absorbing and distributing the load to prevent direct stress concentration on the connection terminal, thereby preventing deformation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If passive elements are integrated into the semiconductor package, then functionality is improved, but void formation occurs due to uneven stress distribution

Engineering Contradiction:
ImprovefunctionalityVSAvoidvoid formation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Different regions of the upper insulating layer are assigned different local qualities and functions: the dam region provides mechanical support and stress distribution, the insulating structure region provides electrical isolation and spacing, and the exposed base portion region provides structural continuity. This local differentiation ensures uniform stress distribution throughout the package, preventing void formation.

Inventive Principle:
Principle #3Local quality

3Reliability

If the upper insulating layer completely covers the base portion, then insulation is improved, but stress distribution becomes uneven causing deformation

Engineering Contradiction:
ImproveinsulationVSAvoidstress distribution
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The upper insulating layer is segmented to create three distinct functional regions: a dam region that contacts the passive element for stress distribution, an insulating structure region spaced apart for electrical isolation, and an exposed base portion region that allows stress relief. This segmentation simultaneously achieves adequate insulation while maintaining uniform stress distribution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different local qualities are applied to different regions of the insulating layer structure. The dam region has high mechanical support quality, the insulating structure region has high electrical isolation quality, and the exposed base portion has stress relief quality. This local quality differentiation resolves the contradiction between insulation and stress distribution.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250022866A1Semiconductor package
Publication Date: 2025.01.16 SAMSUNG ELECTRONICS CO LTD
  • US20250022866A1 patent drawing
  • US20250022866A1 patent drawing
  • US20250022866A1 patent drawing

AI summary

A semiconductor package includes a substrate, a passive element on the substrate, and a connection terminal connecting the substrate to the passive element. The substrate includes a base portion comprising an element pad connected to the connection terminal, and an upper insulating layer on the base portion to expose at least a portion of the base portion. The passive element is in contact with the upper insulating layer, and a thickness of the connection terminal and a thickness of the upper insulating layer are equal to each other.