Multi-Level Passive Element Memory Cell Read Method
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Solution Overview
Problem
In three-dimensional passive element memory arrays, reading and writing multi-level memory cells require multiple cycles, leading to performance penalties due to the need for multiple write and read operations and the limitations of these arrays.
Innovation Solution
A method for reading multi-level passive element memory cells using at least two different combinations of reference current levels and read bias voltages to discriminate between four memory cell states, allowing for efficient sensing of current on a selected bit line without the need for multiple stabilizations, thereby reducing the number of read cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sensing methods with exponentially stepped current levels are used to read four-level memory cells, then measurement precision is improved, but read cycle time increases due to multiple stabilization delays
Solution Approach 1:
The patent changes the sensing parameters by using multiple combinations of reference current levels and read bias voltages instead of traditional exponentially stepped current levels. This allows discrimination of four memory cell states through two read cycles with different parameter sets, reducing the need for multiple stabilization delays while maintaining measurement precision.
2Manufacturing precision
If multiple write cycles are used to program multi-level memory cells, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent applies partial action by using only two read cycles with different parameter combinations to sufficiently discriminate four memory cell states, rather than using more cycles. This reduces the total operation time while maintaining the ability to accurately read all four levels, thereby improving productivity without sacrificing manufacturing precision.
3Measurement precision
If multiple read cycles with stabilization delays are used, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent maintains continuous useful action by performing two read cycles with different parameter combinations back-to-back without requiring intermediate stabilization delays. This continuous operation reduces the total time the sensing circuitry is active, thereby reducing power dissipation while still achieving the necessary measurement precision through the different parameter sets.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more efficient reading of multi-level passive element memory cells by using fewer read cycles, improving performance and reducing power dissipation in memory arrays.
Implementation Method 1
A memory array is disclosed including a plurality of multi-level two-terminal passive element memory cells, each connected between an associated word line and an associated bit line and each having first, second, third, and fourth memory cell states corresponding respectively to first, second, third, and fourth decreasing resistance levels
Implementation Method 2
The memory array further includes means for discriminating between the four memory cell states by sensing current on a selected bit line for at least two different combinations of reference current level and read bias voltage on the selected bit line
Data Source
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AI summary
A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.