Passive Element Structure With Tunable Parasitic Capacitance
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Solution Overview
Problem
Semiconductor devices operating in frequency bands exceeding 100 GHz face challenges due to manufacturing variations affecting passive elements, leading to significant deterioration of high-frequency characteristics, particularly in analog and high-frequency circuits.
Innovation Solution
The semiconductor device incorporates embedded semiconductors with low- and high-concentration impurity regions beneath passive elements, allowing for independent adjustment of parasitic capacitance through controlled voltage application, thereby stabilizing the characteristic impedance and improving high-frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a correction circuit is added to adjust impedance of passive elements, then manufacturing variations can be corrected, but the correction circuit affects analog circuit performance and high-frequency characteristics deteriorate
Solution Approach 1:
The patent extracts the impedance adjustment function from a separate correction circuit and integrates it directly into the passive element structure itself. By forming variable capacitance regions within the interlayer insulating film beneath the passive element, the impedance adjustment capability is embedded within the passive element, eliminating the need for external correction circuits that would affect analog circuit performance.
Solution Approach 2:
The patent merges the impedance adjustment function with the passive element structure by combining the variable capacitance regions with the interlayer insulating film. This integration allows the passive element to self-adjust its impedance characteristics without requiring separate correction circuitry, thereby maintaining high-frequency performance while achieving manufacturing variation compensation.
2Object-affected harmful factors
If the p-type layer is maintained at high resistance without wells, then substrate noise is reduced, but manufacturing variations still affect passive element performance at high frequencies
Solution Approach 1:
The patent applies local quality by creating variable capacitance regions with specific dielectric constant variations in localized areas within the interlayer insulating film, directly beneath the passive element. This allows impedance adjustment in the specific region affecting passive element performance while maintaining high resistance of the p-type layer overall, thus reducing substrate noise while compensating for manufacturing variations.
Solution Approach 2:
The patent changes the physical parameters of the interlayer insulating film by introducing variable capacitance regions with different dielectric constants. This parameter change enables dynamic adjustment of the electric field distribution and impedance characteristics of passive elements, compensating for manufacturing variations without requiring changes to the p-type layer resistance structure.
3Productivity
If pattern miniaturization is advanced for logic circuits, then device density increases, but passive element performance deteriorates at frequencies above 100 GHz
Solution Approach 1:
The patent addresses high-frequency performance deterioration by moving the impedance adjustment mechanism from the planar dimension to the vertical dimension. By forming variable capacitance regions within the interlayer insulating film structure, the solution utilizes the third dimension (film thickness direction) to control electromagnetic field distribution, enabling effective impedance adjustment for miniaturized passive elements operating at frequencies above 100 GHz without compromising device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively mitigates the impact of manufacturing variations on high-frequency characteristics by dynamically adjusting parasitic capacitance, ensuring stable operation in frequency bands of several tens of GHz and beyond.
Implementation Method 1
embedded semiconductors with low- and high-concentration impurity regions beneath passive elements, allowing for independent adjustment of parasitic capacitance through controlled voltage application
Data Source
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AI summary
A semiconductor device includes: a semiconductor substrate (1); a first oxide film (2) formed on a surface of the semiconductor substrate (1); a first oxide film (3) formed on a surface of the first oxide film (2); a passive element (10) formed inside the first oxide film (3); and embedded semiconductors (21) to (23) embedded in a surface of the first oxide film (2) directly below the passive element (10) and including low-concentration impurity regions (21a) to (23a) in which an interface is formed with a back surface of the first oxide film (3), and high-concentration impurity regions (21b) to (23b) bonded to bottom surfaces of the low-concentration impurity regions (21a) to (23a) and having contact surfaces which are exposed to a surface of the first oxide film (3) and to which a voltage is applied, respectively.