Passive Equalizer Layout for High-Speed SerDes Fan-Out
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Solution Overview
Problem
Conventional passive equalizers in SerDes communication systems face limitations in meeting high-speed interconnection requirements due to low working frequencies and occupancy of valuable fan-out space on packages or PCBs, leading to reduced fan-out density and additional power consumption.
Innovation Solution
An equalization circuit design that integrates a receiver impedance network within the receiver chip and a passive equalizer outside the chip, connected via connectors, allowing adjustable bandwidth gain and eliminating the need for surface-mount devices, thus increasing working frequency without occupying additional chip area or fan-out space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a passive equalizer is constructed outside the chip using surface-mount devices, then equalization function is provided, but working frequency is limited and cannot meet high-speed SerDes interconnection requirement
Solution Approach 1:
The patent merges the passive equalizer with the package substrate by fabricating the equalizer circuit (comprising resistors, inductors, and capacitors) directly on the package substrate. This integration eliminates the need for separate surface-mount devices while enabling higher working frequencies through reduced parasitic effects and improved signal integrity, thus resolving the contradiction between manufacturing ease and frequency performance.
2Reliability
If a passive equalizer is placed on package or PCB, then equalization is achieved, but fan-out space is occupied and fan-out density is reduced
Solution Approach 1:
The patent relocates the passive equalizer from the traditional planar position on the package top surface to the package substrate layer. This dimensional relocation allows the equalizer to coexist with fan-out structures in the vertical dimension, eliminating space conflicts and maintaining high fan-out density while preserving signal quality through effective equalization.
3Reliability
If an active equalizer is disposed inside the chip, then equalization is provided, but additional power and chip area are consumed
Solution Approach 1:
The patent extracts the equalizer function from the active equalizer inside the chip and implements it as a passive equalizer on the package substrate. This extraction eliminates the need for additional power consumption associated with active components while maintaining equalization capability, thus resolving the contradiction between signal quality and power consumption.
Data Source
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AI summary
An equalization circuit is provided, including a receiver impedance network (Zt) disposed inside a receiver chip (RX), and a passive equalizer (100) disposed outside the receiver chip (RX). The receiver impedance network (Zt) is connected to the passive equalizer (100) by a first connector (201) and a second connector (202), and is connected to a first trace (203) and a second trace (204) of a differential trace by the first connector (201) and the second connector (202) respectively. The differential trace is configured to connect the receiver chip (RX) and a transmitter chip (TX). An package apparatus and a data transmission apparatus are provided. The receiver impedance network (Zt) and the passive equalizer (100) are connected by the first connector (201) and the second connector (202), so that the receiver impedance network (Zt) and the passive equalizer (100) work cooperatively, and a resistance value of the receiver impedance network (Zt) is adjusted to implement an adjustable receiver bandwidth gain, thereby increasing a working frequency. The passive equalizer (100) is disposed outside the receiver chip (RX) and is connected to the first connector (201) and the second connector (202), and therefore does not occupy additional fan-out space or an additional chip area.