Passive-Hold MDAC Circuit for Low-Power High-Speed ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-speed, high-resolution analog-to-digital converters face challenges with high power consumption due to sample-and-hold circuits and suffer from clock skew and bandwidth mismatch errors in sample-and-hold-less architectures.
Innovation Solution
A multiplying digital-to-analog conversion circuit with a passive sample-and-hold mode that integrates a capacitor, switches between input voltage and reference voltage, and uses a feedback amplifier to produce a residue signal, eliminating the need for additional amplifier power and addressing clock skew and bandwidth mismatch issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a sample-and-hold circuit is used in conventional pipeline ADC, then high-speed and high-resolution conversion is achieved, but power consumption increases significantly
Solution Approach 1:
The patent implements periodic switching between sampling mode and hold mode using phase signals (phi1, phi2, phi3). The sample-and-hold circuit operates periodically, switching between active sampling phase and passive hold phase, thereby reducing average power consumption while maintaining high-speed conversion capability. The periodic activation of the amplifier only during necessary phases reduces energy dissipation compared to continuous operation.
Solution Approach 2:
The patent employs dynamic switching of the sample-and-hold circuit between different operational states (sampling, holding, amplification) based on the conversion phase. The circuit transitions from a static always-on design to a dynamic state-machine approach where the amplifier is activated only when needed, reducing overall power consumption while maintaining performance.
2Use of energy by moving object
If sample-and-hold-less architecture is used to reduce power consumption, then power consumption decreases, but clock skew and bandwidth mismatch errors occur
Solution Approach 1:
The patent merges the sample-and-hold function with the MDAC (multiplying digital-to-analog converter) by integrating the holding capacitor directly into the MDAC structure. This unified design eliminates the need for separate sampling paths for MDAC and sub-ADC, thereby avoiding clock skew and bandwidth mismatch errors while maintaining reduced power consumption compared to traditional separate sample-and-hold circuits.
Solution Approach 2:
The patent implements feedback mechanisms where the hold circuit receives control signals based on the quantization results from the sub-ADC. This feedback ensures that the holding operation is synchronized with the conversion process, maintaining accuracy by preventing clock skew effects and ensuring proper timing relationships between different conversion stages.
3Measurement precision
If active amplification is used in sample-and-hold circuit, then sampling accuracy is maintained, but power consumption increases
Solution Approach 1:
The amplifier is activated periodically only during the amplification phase (controlled by phi3 signal) rather than continuously during sampling and hold phases. This periodic activation maintains sampling accuracy when needed while dramatically reducing average power consumption by keeping the amplifier in a low-power state during other phases of the conversion cycle.
Solution Approach 2:
The sample-and-hold circuit dynamically switches between active amplification mode and passive holding mode. During the hold phase, the circuit operates passively without active amplification, maintaining the sampled voltage through capacitor charge storage. The amplifier is dynamically activated only during the brief amplification phase, reducing power consumption while maintaining accuracy when required.
Data Source
AI summary
A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.