Passive Integration Substrate for IC Power Routing
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Solution Overview
Problem
The increasing number of input and output pins on integrated circuits (ICs) and the associated power distribution and decoupling capacitors occupy a significant area, limiting miniaturization and efficiency due to space congestion and parasitic inductive effects, which are not optimally addressed by current interconnection techniques and semiconductor technologies.
Innovation Solution
An integrated circuit assembly with a passive integration substrate on top of the IC, featuring dedicated zones for power and ground connections, integrated capacitors, and a decoupling capacitor to manage voltages, reducing the need for external components and minimizing parasitic inductive effects, while also acting as a heat spreader.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power distribution and decoupling capacitors are integrated within the IC, then power consumption and heat dissipation improve, but the IC area occupied by power routing and capacitors increases
Solution Approach 1:
The patent moves power distribution and decoupling functions from the planar IC surface to a three-dimensional stacked architecture. Passive components (capacitors, inductors, resistors) are integrated on a separate substrate that is vertically stacked above the IC core, utilizing the Z-dimension to eliminate area congestion on the IC surface while maintaining electrical connectivity through through-silicon vias and substrate interconnections.
Solution Approach 2:
The patent introduces an intermediate passive component substrate as a mediator between the IC core and external power sources. This substrate contains integrated passive components that act as intermediaries to provide on-chip power distribution, decoupling, and filtering functions, thereby reducing the need for external discrete components while minimizing the area occupied on the IC itself.
2Adaptability or versatility
If the number of I/O pads increases to support more functions, then IC functionality improves, but the pad ring area increases and core size is constrained
Solution Approach 1:
The patent relocates I/O pad functions from the two-dimensional pad ring to a three-dimensional stacked architecture. Additional I/O functionality is achieved by adding more pads on the passive component substrate above the IC core, utilizing vertical stacking to expand I/O capacity without increasing the footprint of the pad ring or constraining the core area.
3Reliability
If external decoupling capacitors are used for frequency decoupling, then decoupling performance improves, but parasitic inductive effects increase and external components are required
Solution Approach 1:
The patent merges the decoupling capacitor with the IC package structure by integrating it on the passive component substrate that is vertically stacked above the IC core. This integration minimizes the loop area between the power source and the IC, thereby reducing parasitic inductance while maintaining effective decoupling performance across frequency ranges.
Solution Approach 2:
The integrated passive component substrate acts as an intermediary that provides decoupling capacitance close to the IC core through vertical interconnections. This intermediate structure reduces the parasitic inductance associated with external capacitor connections while maintaining the necessary decoupling performance.
4Reliability
If interconnection techniques are used to connect IC to PCB, then electrical connectivity is achieved, but miniaturization is limited due to larger connection areas
Solution Approach 1:
The patent transitions from two-dimensional planar interconnection to three-dimensional vertical stacking. The passive component substrate is connected to the IC core through vertical through-silicon vias and substrate interconnections, enabling compact package sizing by utilizing the vertical dimension for signal and power routing rather than requiring large planar connection areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the physical size of the IC by relocating power and ground routing, minimizes parasitic inductive effects, and enhances heat dissipation, allowing for more complex IC designs or smaller packages without compromising performance.
Implementation Method 1
acting as a heat spreader
Data Source
AI summary
An integrated circuit assembly (ICA) comprises: a digital and/or analog integrated circuit (S1) having a core with input and/or output pins and at least one power supply connection pad (PP) and one ground connection pad (GP) connected to a chosen one of the input and/or output pins and respectively connected to power supply and ground connection zones (MZ1) of a printed circuit board (PCB), and a passive integration substrate (S2) set on top of the digital and/or analog integrated circuit (S1) and comprising i) at least first and second input zones respectively connected to the ground (GP) and power supply (PP) connection pads to be fed with input ground and supply voltages, ii) input and/or output zones connected to chosen core input and/or output pins, and Ëi) a passive integrated circuit (PIC) connected to the first and second input zones and arranged to feed the substrate input and/or output zones with chosen ground and supply voltages defined from the input ground and supply voltages.