Passive Sample-and-Hold MDAC for Low-Power Pipeline ADCs
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Solution Overview
Problem
Conventional high-speed, high-resolution analog-to-digital converters with switched-capacitor pipeline architectures face challenges in power consumption due to sample-and-hold circuits and suffer from clock skew and bandwidth mismatch issues in S/H-less designs, leading to errors in ADC output.
Innovation Solution
A multiplying digital-to-analog conversion circuit with a passive sample-and-hold mechanism, where a capacitor is connected to an input voltage during a sampling phase, a fixed reference voltage during a hold phase, and an amplifier produces a residue signal in an amplify phase, eliminating the need for additional amplifier power and addressing clock skew and bandwidth mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sample-and-hold circuit is used in conventional pipeline ADC architecture, then high-speed and high-resolution conversion is achieved, but power consumption increases significantly
Solution Approach 1:
The invention extracts and removes the active sample-and-hold amplifier from the ADC architecture, replacing it with a passive capacitor-based sampling mechanism. This eliminates the high power consumption associated with active amplification while maintaining the necessary sampling function through charge storage on capacitors during the sampling phase.
Solution Approach 2:
The invention replaces the active electronic amplification system (sample-and-hold amplifier) with a passive electrical storage system (capacitors). The capacitors store the sampled voltage charge during the sampling phase without requiring active power consumption, thus substituting an active system with a passive one.
2Use of energy by moving object
If sample-and-hold circuit-less ADC architecture is used to reduce power consumption, then power consumption decreases, but clock skew and bandwidth mismatch errors occur
Solution Approach 1:
The invention merges the sampling function and the hold function into a single integrated capacitor-based sample-and-hold mechanism. The same capacitor that samples the input signal also holds the charge during the quantization phase, eliminating the need for separate sampling paths and thus preventing clock skew and bandwidth mismatch errors.
Solution Approach 2:
The capacitor in the invention serves multiple functions: it acts as the sampling element, the holding element, and the input to the quantizer. This multi-functionality eliminates the need for separate dedicated sampling and holding circuits, thereby avoiding the timing skew and bandwidth mismatch problems that arise from separate paths.
3Use of energy by moving object
If passive sample-and-hold circuit is used, then power consumption is reduced, but additional amplifier power may be required
Solution Approach 1:
The amplifier is operated in a periodic manner, being activated only during the amplify phase after sampling and quantization are complete. During the sampling and hold phases, the amplifier remains inactive. This periodic operation reduces the overall power consumption compared to continuous amplification, while still providing the necessary signal amplification when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption and eliminates errors by integrating a passive sample-and-hold circuit, improving the accuracy and efficiency of the ADC output without increasing analog power consumption.
Implementation Method 1
an input block (2) comprising a capacitor (C) and arranged for switchably connecting said capacitor to an input voltage signal (VIN) at a first terminal of said capacitor (C) during a first phase
Implementation Method 2
an amplifier (7) arranged to be connected to the second terminal of said capacitor (C) and to produce at an amplifier output during the third phase a residue signal corresponding to a linear combination of the input voltage signal (Vin) and the analog voltage derived from the quantized version
Data Source
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AI summary
The present invention relates to a multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter, comprising - an input block (2) comprising a capacitor (C) and arranged for switchably connecting said capacitor to an input voltage signal (VIN) at a first terminal of said capacitor (C) during a first phase and to a fixed reference voltage (VCM) at said first terminal of said capacitor (C) during a second phase, - a sub-analog-to-digital conversion circuit (4) connected to a second terminal of said capacitor (C) and arranged for quantizing a voltage on said capacitor during said second phase and arranged to output a quantized version (DOUT) of said voltage on said capacitor, - a sub-digital-to-analog conversion circuit (5) arranged to receive said quantized version of said voltage and to output an analog voltage derived from said quantized version, wherein said first terminal of said capacitor (C) is arranged to switchably connect to said analog voltage during a third phase, - a feedback block (6) comprising - an amplifier (7) arranged to be connected to said second terminal of said capacitor (C) and to produce at an amplifier output during said third phase a residue signal corresponding to a linear combination of said input voltage signal (Vin) and said analog voltage derived from said quantized version, and - a feedback circuit (8) comprising a feedback capacitor (Cfb) arranged to be connected to said input voltage during said first phase, arranged to have at least one terminal floating during said second phase and arranged to connect to said amplifier output during said third phase.