Passive Mixer Input Resistance for Wider 60 GHz LNA Matching
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Solution Overview
Problem
Designing high-speed analog circuits for 60 GHz operation in 8 layer 40 nm CMOS process is challenging due to energy losses and the need to meet WiGig specifications, with conventional techniques often wasting energy and introducing parasitic elements that hinder performance.
Innovation Solution
The solution involves a common source LNA interfacing with a mixer, using series peaking inductors and adjusting the width of cascode devices to minimize power dissipation, reduce the quality factor of the resonant circuit, and eliminate the need for capacitive or resistive arrays, thereby increasing bandwidth and meeting WiGig requirements at reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional techniques are used for high frequency circuit design, then the circuit can operate at 60 GHz, but energy losses increase and parasitic elements are introduced
Solution Approach 1:
The patent changes the impedance parameter of the mixer input to transform it from a capacitive load to a resistive load, which reduces energy losses and improves power efficiency while maintaining 60 GHz operation
Solution Approach 2:
The patent applies different impedance transformation techniques at different stages: the LNA output is transformed to match the mixer's resistive input, while the mixer's capacitive load is transformed to appear resistive to the LNA, optimizing each interface locally
2Speed
If conventional techniques are used for high frequency circuit design, then the circuit can operate at 60 GHz, but parasitic elements are introduced that hinder performance
Solution Approach 1:
The patent converts the harmful capacitive loading effect into a beneficial resistive load by using impedance transformation, where the mixer's inherent capacitive elements are transformed to appear as resistive loads, eliminating the need for additional compensation components
Solution Approach 2:
The patent extracts and eliminates parasitic capacitive effects from the signal path by transforming them into resistive equivalents, removing the harmful influence of these parasitic elements on circuit performance
3Device complexity
If the mixer presents a capacitive load to the LNA, then the LNA can be designed simply, but the overall system power efficiency deteriorates
Solution Approach 1:
The patent changes the effective load parameter seen by the LNA from capacitive to resistive through impedance transformation, improving power efficiency without significantly increasing LNA design complexity
Solution Approach 2:
The patent introduces an impedance transformation network as an intermediary between the LNA and mixer, which transforms the capacitive load into a resistive load, improving power efficiency while keeping the LNA design relatively simple
4Ease of manufacture
If high speed analog circuits are designed in 8 layer 40 nm CMOS process, then integration is improved, but energy losses increase due to process limitations
Solution Approach 1:
The patent changes the load impedance parameter to resistive, which reduces energy losses in the 40 nm CMOS process by minimizing reactive power circulation and improving power efficiency
Solution Approach 2:
The patent converts the harmful effect of capacitive loading and associated energy losses into a beneficial resistive load condition, where energy is dissipated efficiently and power consumption is reduced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes power dissipation, increases bandwidth, and allows the receiver to meet WiGig specifications by optimizing the LNA's noise figure and center frequency, while reducing unnecessary parasitic elements and energy losses.
Implementation Method 1
series peaking inductor coupling the cascode devices of the LNA together
Data Source
AI summary
A common-source Low Noise Amplifier (LNA) comprises a first spiral inductor coupled to a source of a first transistor, a second spiral inductor coupled to a drain of a second transistor, and a third inductor connecting the first transistor to the second transistor. The third inductor is configurable to enable a first capacitance to be coupled in parallel to form a bandpass filter. The first spiral inductor is configurable to enable a second capacitance to be coupled in parallel to form a resonant circuit. A variation of the LNA further includes a drain of a third transistor coupled to a gate of a fourth transistor with a first width, a source of the third transistor coupled to the resonant circuit, and an oscillator clock configured to operate at a first frequency that enables the third transistor, wherein the third transistor presents a first impedance to the resonant circuit, causing the resonant circuit to have a first bandwidth.