Wafer-Level Bonding for Passive Alignment of Photonic Dies
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Solution Overview
Problem
Current methods for manufacturing photonic devices require complex active alignment of each photonic IC, leading to increased production costs, time, susceptibility to variance, and inefficiencies in optical signal coupling between silicon photonics devices and optical fibers.
Innovation Solution
Employing wafer-on-wafer bonding techniques to align a receptacle wafer with a photonic IC wafer, utilizing lithography alignment features for precise optical alignment, and etching mechanical features to reduce height and complexity, allowing for passive alignment of multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If active alignment of each photonic IC is performed, then optical signal coupling precision is improved, but production time and cost increase
Solution Approach 1:
The patent applies preliminary action by forming mechanical alignment features (such as alignment marks, protrusions, or recesses) on the photonic ICs and receptacles before final assembly. These features are created during the fabrication process itself, allowing alignment to be built-in rather than performed separately during assembly, thus eliminating time-consuming active alignment steps while maintaining precision
Solution Approach 2:
The mechanical alignment features enable the photonic ICs and receptacles to self-align during assembly. The features themselves perform the alignment function through their physical geometry, eliminating the need for complex active alignment procedures. This self-service approach reduces production time while maintaining the required optical coupling precision
2Manufacturing precision
If active alignment of each photonic IC is performed, then optical signal coupling precision is improved, but production cost increases
Solution Approach 1:
The alignment features are formed during the standard photonic IC fabrication process using existing lithography and etching equipment, rather than requiring separate alignment machinery. This integrates alignment capability into the manufacturing flow at minimal additional cost, reducing overall production expenses while maintaining precision
Solution Approach 2:
The mechanical alignment features enable passive alignment during assembly, eliminating the need for expensive active alignment equipment and labor. The features themselves provide the alignment function through their physical geometry, significantly reducing manufacturing costs while maintaining optical coupling precision
3Manufacturing precision
If active alignment of each photonic IC is performed, then optical signal coupling precision is improved, but manufacturing complexity increases
Solution Approach 1:
The alignment features are created during the fabrication process using standard photonic IC manufacturing steps, integrating alignment capability into the existing manufacturing flow. This approach avoids adding separate complex alignment procedures and equipment, reducing overall manufacturing complexity while maintaining precision
Solution Approach 2:
The mechanical alignment features enable passive alignment during assembly, eliminating the need for complex active alignment procedures. The features themselves provide the alignment function through their physical geometry, significantly simplifying the manufacturing process while maintaining optical coupling precision
4Manufacturing precision
If multiple photonic ICs are manufactured using conventional methods, then production scalability is limited, but manufacturing precision is maintained
Solution Approach 1:
The patent merges multiple photonic ICs and receptacles onto a single wafer substrate, enabling parallel fabrication and assembly of multiple devices simultaneously. This wafer-level integration allows for scalable production while maintaining alignment precision through the shared mechanical alignment features formed during the same fabrication process
Solution Approach 2:
Mechanical alignment features are formed on all photonic ICs and receptacles during the wafer fabrication process before final assembly. This preliminary formation of alignment features across the entire wafer enables precise alignment to be built-in for all devices simultaneously, supporting both high precision and scalable production
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces production variance, lowers assembly costs, improves optical performance, and decreases power consumption by enabling scalable, repeatable, and cost-effective manufacturing of optically aligned receptacle and photonic IC stacks.
Implementation Method 1
wafer-on-wafer bonding techniques to align a receptacle wafer with a photonic IC wafer
Implementation Method 2
utilizing lithography alignment features for precise optical alignment
Implementation Method 3
etching mechanical features to reduce height and complexity
Data Source
AI summary
Some embodiments of the present disclosure are directed to wafer alignment in multiple dies. For example, a receptacle wafer and a photonic wafer may be prepared containing a plurality of individual dies. Further, these two wafers may be aligned, wafer bonded, and cut into the individual dies. Additionally, or alternatively, these individual dies may be ready to be attached to a substrate and require no further alignment. The method of the present disclosure may be (i) cost effective since a single, passive receptacle wafer alignment results in multiple dies, (ii) repeatable (e.g., less variance in production) since it utilizes silicon lithography alignment features and scalable silicon WOW assembly, and (iii) improve optical performance since the thin receptacle wafer has a lower height resulting in a shorter optical path.