10 Gbps Network TAP Using Passive Transceiver Interconnect

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Solution Overview

Problem

Conventional network TAPs for 10-Gigabit Ethernet are costly, unreliable, and require complex thermal management due to the use of high-end Ethernet switching IC chips, which have short production lifespans and are not cost-effective for widespread use.

Innovation Solution

A network TAP design utilizing four serial Ethernet transceivers interconnected via PCB traces to create a passive tap circuit arrangement, eliminating the need for Ethernet switching IC chips and enabling operation up to 10 Gbps without heat-related issues, using SFP/SFP+ transceiver modules for flexibility and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-end Ethernet switching IC chips are used to implement 10-Gigabit Ethernet TAP, then the TAP can achieve 10 Gbps data rate, but the cost increases significantly and thermal management becomes complex

Engineering Contradiction:

Improvedata rateVSAvoidthermal management complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent divides the monolithic Ethernet switching IC chip into separate functional components: four independent serial Ethernet transceivers (two for pass-through ports, two for monitor ports) interconnected via PCB traces. This segmentation eliminates the need for a single high-end switching IC, reducing thermal management complexity while maintaining 10 Gbps capability through the distributed transceiver architecture

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts the switching function from the integrated Ethernet switching IC chip and replaces it with a passive PCB trace-based interconnection system. By taking out the active switching IC component, the design eliminates the associated thermal management requirements while preserving the essential packet switching and port mirroring functions through the passive trace network

Inventive Principle:

Principle #2Taking out (Extraction)

2Speed

If high-end Ethernet switching IC chips are used to implement 10-Gigabit Ethernet TAP, then the TAP can achieve 10 Gbps data rate, but the material cost increases significantly

Engineering Contradiction:

Improvedata rateVSAvoidmaterial cost

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The patent replaces expensive, high-end Ethernet switching IC chips with inexpensive, commercially available serial Ethernet transceivers that can be sourced at lower cost. The design accepts that these individual transceivers may have shorter production lifecycles but achieves significant material cost reduction, making the overall TAP system more cost-effective while maintaining 10 Gbps performance

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Adaptability or versatility

If Ethernet switching IC chips are used to implement TAP, then port mirroring function is achieved, but the production lifespan of the TAP is limited by chip availability

Engineering Contradiction:

Improveport mirroring capabilityVSAvoidproduction lifespan

Core Design Contradiction:

Adaptability or versatilityVSDuration of action of stationary object

Solution Approach 1:

The patent implements port mirroring functionality through a universal, passive PCB trace-based architecture that can accommodate different transceiver types and configurations. This universal design approach, using standard interconnection practices rather than proprietary IC chip functions, extends the production lifespan of the TAP by decoupling the port mirroring capability from specific chip availability cycles

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Device complexity

If passive tap circuit arrangement with serial Ethernet transceivers is used, then cost and complexity are reduced, but data rate must be maintained at 10 Gbps

Engineering Contradiction:

Improvecircuit arrangement complexityVSAvoiddata rate

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent changes the operational parameters of the serial Ethernet transceivers to support 10 Gbps data rates. By selecting transceivers with appropriate bandwidth characteristics and optimizing the PCB trace impedance and length matching, the design achieves high-speed operation despite using a simpler, passive circuit arrangement rather than a complex integrated switching IC

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20230208741A1Network tap capable of tapping a 10gbps network link

Publication Date: 2023.06.29 HE ZIQIANG

AI summary

A network TAP includes four serial transceivers on a printed circuit board. Each serial transceiver has a medium-dependent interface and a serial differential interface that includes a differential input and a differential output. A passive tap circuit arrangement is configured to be operative at up to 10 Gbps or a higher data rate and configures the differential output signal from the differential output of the first serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the second and third serial transceivers. It also configures the differential output signal from the differential output of the second serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the first and fourth serial transceivers. In one embodiment according to the present invention, the four serial transceivers are pluggable transceiver modules.