Passive Variable Resistance Memory for State Retention
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Solution Overview
Problem
Existing methods for saving and restoring state information in integrated circuits, such as flip-flops and processors, require significant power and additional design complexity, leading to inefficiencies and increased costs, especially during power gating modes where parts of the chip are powered down to conserve energy.
Innovation Solution
The use of passive variable resistance memory cells, which can store complementary state information from active memory circuits and restore it without the need for a separate power supply, allowing for efficient power gating by capturing data in non-volatile cells and reducing the complexity of separate read and write circuitries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flip-flops and active memory circuits are used to store state information, then fast access and retrieval is achieved, but power consumption increases and data is lost during power gating
Solution Approach 1:
The patent applies preliminary action by capturing and storing state information from active memory circuits into non-volatile passive variable resistance memory cells before power gating occurs. This pre-capture mechanism ensures that state data is preserved in a non-volatile medium, allowing the active circuits to be powered down without data loss, thus resolving the contradiction between maintaining fast state access and reducing power consumption during idle periods
Solution Approach 2:
The patent implements copying by creating a duplicate copy of the state information from active memory circuits into passive non-volatile memory cells. This copying mechanism allows the original active memory to be powered down while the copied state data remains intact in the passive memory, enabling both power savings and rapid state restoration when needed
2Reliability
If separate read and write circuitries are implemented for state backup, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by combining the read and write operations into a single unified mechanism. The passive variable resistance memory cells inherently maintain their stored state without requiring separate read/write circuitry, as the resistance state itself serves as the stored information. This eliminates the need for complex separate read and write paths, reducing overall device complexity while maintaining reliable data retention
Solution Approach 2:
The patent implements self-service by designing the passive variable resistance memory cells to automatically retain their state information without requiring active maintenance or separate control circuitry. The cells inherently preserve their resistance states through their physical properties, eliminating the need for external read/write management and simplifying the overall system architecture
3Use of energy by moving object
If non-volatile memory cells are used for state storage, then power consumption is reduced, but access speed decreases
Solution Approach 1:
The patent applies preliminary action by pre-capturing state information into non-volatile memory cells before power gating. When power is restored, the state restoration process begins immediately from the pre-stored data, minimizing the effective access time. This pre-positioning of data in non-volatile memory allows the system to leverage the low power consumption of passive cells while maintaining fast restoration performance through the readiness of pre-captured state information
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more efficient state saving and restoration, reducing power consumption and design complexity, allowing for seamless transitions between power states without losing data, and is more compact and cost-effective compared to conventional methods.
Implementation Method 1
at least one passive variable resistance memory (PVRM) cell operative to backup data from the active memory circuit
Data Source
AI summary
A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.