Path-Based Crosstalk Fault Test Scanning for Delay Defect Detection
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Solution Overview
Problem
Conventional fault models and ATPG tools inadequately test for accumulative crosstalk along paths in silicon validation and manufacturing, failing to detect delay defects in long parallel nets effectively as technology scales down.
Innovation Solution
A path-based crosstalk fault model combined with built-in self-test (BIST) and automatic test pattern generation software, allowing for full controllability of target paths and aggressor nets to detect and validate delay defects on long parallel nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fault models and ATPG tools are used, then testing is simpler and faster, but they fail to detect accumulative crosstalk delay defects on long parallel nets
Solution Approach 1:
The patent segments the testing approach by introducing a path-based fault model that divides the net into segments with different crosstalk characteristics (near-end, mid-range, far-end). This allows targeted testing of accumulative crosstalk effects on long parallel nets while maintaining manageable test complexity through structured test pattern generation.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing crosstalk delay values for different path segments during design time. These pre-computed values are used during testing to quickly identify accumulative crosstalk defects without requiring complex real-time calculations, thus improving detection capability while controlling test complexity.
2Speed
If technology scaling continues, then device size decreases and speed increases, but crosstalk-induced delay defects become more significant and harder to detect
Solution Approach 1:
The patent transitions from conventional discrete net testing to a path-based dimensional approach that considers the spatial dimension of signal propagation along long parallel nets. By modeling crosstalk accumulation across multiple segments and positions along the net path, the method detects delay defects that become significant with technology scaling and increased processing speeds.
Solution Approach 2:
The patent applies parameter changes by introducing path-specific parameters such as segment length, aggressor-victim net configurations, and cumulative crosstalk delay values. These parameters are adjusted based on the specific long parallel net being tested, allowing the model to accurately capture crosstalk effects that worsen with technology scaling while maintaining detection sensitivity.
3Device complexity
If discrete net fault models are used, then testing is simpler, but they cannot capture accumulative crosstalk effects along victim paths
Solution Approach 1:
The patent merges multiple discrete net fault models into a unified path-based model that combines the characteristics of all nets along a victim path. This integration allows the model to capture accumulative crosstalk effects from multiple aggressors while maintaining a structured approach that balances measurement precision with manageable complexity through systematic test pattern generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective detection and validation of delay defects on long parallel nets by maximizing switching activity and controlling aggressor nets, improving defect detection during silicon validation.
Implementation Method 1
capacitive coupling and/or mutual inductance originates
Implementation Method 2
capacitive coupling and/or mutual inductance originates
Data Source
AI summary
A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.