Path-Based Timing Driven Placement Using Pseudo Nets
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Solution Overview
Problem
Current semiconductor Electronic Design Automation (EDA) techniques, specifically half-perimeter wire length (HPWL) methods, are not timing aware, leading to insufficient timing compliance in integrated circuit designs, and previous attempts to address this issue have been computationally intensive, prone to saturation, and result in tortuous paths.
Innovation Solution
The implementation of path-based timing driven placement using iterative pseudo netlist changes, where timing-critical source-sink paths are identified and new pseudo two-pin nets are created to facilitate revised wire-length-driven placements, improving timing performance through iterative refinements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If HPWL techniques are used for placement, then wire length optimization is achieved, but timing compliance deteriorates
Solution Approach 1:
The patent segments the placement optimization into multiple iterative phases. Each phase identifies specific timing-critical paths and creates targeted pseudo-nets for those paths, rather than treating the entire netlist uniformly. This segmentation allows the placer to focus computational effort on timing-critical regions while maintaining wire length optimization elsewhere.
Solution Approach 2:
The patent introduces pseudo-nets as intermediary elements between actual timing-critical nets and the placer algorithm. These pseudo-nets act as mediators that carry timing information to the wire-length-driven placer, enabling the placer to optimize timing without requiring a complete redesign of the placement algorithm. The pseudo-nets are created iteratively based on timing analysis results.
2Reliability
If timing-aware placement methods are implemented, then timing compliance improves, but computational complexity increases
Solution Approach 1:
The patent applies partial action by creating pseudo-nets only for timing-critical paths rather than all paths in the circuit. The timing analysis identifies a subset of critical paths, and pseudo-nets are generated only for those paths. This partial approach significantly reduces computational complexity compared to analyzing and optimizing all possible signal paths while still achieving timing compliance for the critical paths.
Solution Approach 2:
The patent implements periodic action through iterative placement refinement. The process cycles through timing analysis, pseudo-net creation, and placement optimization in repeated iterations. Each iteration improves timing compliance progressively, allowing the system to converge to an acceptable solution without requiring exhaustive computation in a single pass.
3Reliability
If iterative pseudo netlist changes are performed, then timing performance improves, but processing time increases
Solution Approach 1:
The patent implements feedback through iterative timing analysis and pseudo-net creation. After each placement iteration, timing analysis is performed to identify remaining timing violations, which then inform the creation of new pseudo-nets for the next iteration. This feedback loop allows the system to focus computational effort on resolving specific timing issues as they are identified, improving timing performance efficiently.
Solution Approach 2:
The patent performs preliminary timing analysis to identify critical paths before creating pseudo-nets. By analyzing timing characteristics in advance and pre-identifying critical paths, the system can create targeted pseudo-nets that address the most important timing issues first, reducing the total number of iterations needed and thereby reducing overall processing time.
Data Source
AI summary
Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.