Automated Path Delay Test Vector Generation Using Functional Simulation
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Solution Overview
Problem
Conventional methods for generating path delay test (PDT) test vectors in integrated circuit design often result in less than 60% test coverage due to exponential growth in the number of paths, making them time-consuming and requiring specialized equipment, while existing tools rely on test point and node access, limiting coverage.
Innovation Solution
The method involves generating PDT test vectors through functional simulation of the circuit design, identifying paths without path delay test coverage, and using structural tests to create test vectors that provide comprehensive path delay fault coverage, reducing reliance on automatic test equipment and increasing test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PDT test vector generation methods are used, then test coverage is limited to less than 60%, but the method is simpler and requires less specialized equipment
Solution Approach 1:
The patent segments the test generation process into functional test execution and structural test integration. Functional tests are run first to capture high-level behavior, then structural tests are applied to specific paths identified as uncovered. This segmentation allows comprehensive coverage without requiring a completely complex dedicated PDT system.
Solution Approach 2:
The patent merges functional testing and structural testing into a unified test generation approach. By combining the behavioral validation of functional tests with the path-specific coverage of structural tests, the system achieves high PDT coverage using existing test infrastructure rather than requiring completely separate specialized equipment.
2Reliability
If functional tests are executed by automatic test equipment to increase test coverage, then test coverage percentage increases to above 60%, but test generation becomes time consuming and requires highly specialized capital equipment
Solution Approach 1:
The patent performs preliminary functional simulation to identify which specific paths require PDT testing before actual test execution. By pre-identifying uncovered paths through simulation, the system avoids time-consuming trial-and-error testing and directly targets the paths that need coverage, significantly reducing overall test generation time.
Solution Approach 2:
The patent uses an intermediary representation of the circuit design that links functional test behavior to structural path information. This intermediary model allows the system to translate functional test results into specific path coverage requirements without requiring direct complex interactions between functional test equipment and structural test generators, streamlining the process.
3Reliability
If existing PDT tools rely on test point and node access to generate test vectors, then the tool implementation is simpler, but path delay test coverage remains limited
Solution Approach 1:
The patent creates a universal test generation method that works with both existing test point/node-based tools and new functional simulation approaches. The system can operate with traditional access methods when available while also utilizing functional simulation to identify paths, making the approach broadly applicable without requiring complete tool redesign.
Solution Approach 2:
The patent adds a new dimension to test generation by incorporating functional simulation behavior analysis alongside traditional structural path analysis. This additional dimensional approach allows the system to identify paths that may not be accessible through conventional test point methods alone, achieving higher coverage without abandoning existing methodologies.
Data Source
AI summary
Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit design. The system and methods can systematically and automatically perform functional and structural testing on selected paths of the circuit design and, in turn, generate one or more test vectors to increase PDT test coverage using the results of the structural test on the selected path.