Path-Matched Multiplier-Accumulator Circuit for High Clock Rates
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Solution Overview
Problem
Conventional multiplier-accumulator (MAC) circuits suffer from long time delays due to carry propagation, leading to lower clock rates and increased power consumption, which are exacerbated by the need for additional pipeline stages and data path registers.
Innovation Solution
A multiplier-accumulator circuit with path matching, utilizing a partial product generation module, summation circuitry with carry-save adders, and path matching circuitry to ensure equal data path delays for all bits, eliminating the need for multiple pipeline stages and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional carry propagation adders are used for multiplication and addition operations, then the circuit structure is simple, but the time delay is long and clock rate is low
Solution Approach 1:
The patent segments the addition operation into multiple carry-save adder stages instead of using a single carry propagation adder. The summation circuitry divides the addition of multiple partial products into sequential carry-save stages, where each stage processes a portion of the addition without full carry propagation, thereby reducing the critical path delay and enabling higher clock rates.
2Speed
If additional pipeline stages and data path registers are added to increase clock rate, then the clock rate improves, but power consumption increases
Solution Approach 1:
The patent extracts and removes the unnecessary pipeline stages and data path registers from the conventional MAC circuit. By using carry-save adders that eliminate full carry propagation, the circuit achieves sufficient timing closure without requiring additional pipelining, thereby reducing the number of registers and associated power consumption while maintaining high clock rate.
3Ease of manufacture
If conventional MAC circuit design is used, then the implementation is straightforward, but IR drop is poor and power consumption is high
Solution Approach 1:
The patent applies local quality by using carry-save adders in specific critical paths where carry propagation causes timing and power issues. The summation circuitry selectively employs carry-save addition for partial product summation and accumulation term generation, optimizing the local circuit characteristics in high-current regions to reduce IR drop and power consumption while maintaining overall implementation feasibility.
Data Source
AI summary
A multiplier-accumulator circuit is disclosed, comprising: a partial product generation (PPG) module, summation circuitry and path matching circuitry. The PPG module is configured to receive n multiplicands and n multipliers to generate multiple partial products according to a predefined multiplication algorithm. The summation circuitry coupled to the PPG module comprises S levels of compressors constructed from carry-save adders for summing up the multiple partial products and multiple previous accumulation terms to produce multiple current accumulation terms such that each bit of the multiple current accumulation terms has substantially the same path delay from inputs to outputs of the summation circuitry. The path matching circuitry comprising multiple components that receive a first clock signal to generate a second clock signal. The multiple components comprise either a first number of logic gates connected in series or the same cells as those embedded in the summation circuitry.