Path Prediction for Instruction Cache Power Reduction
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Solution Overview
Problem
Current cache access methods in processors lead to high dynamic power consumption due to parallel access of multiple cache lines for both branch and non-branch instructions, and increased conflict probability in the branch target buffer (BTB) when both types of instructions are stored together.
Innovation Solution
A path prediction method for a set-associative instruction cache that enables selective access of cache lines based on instruction type, using a path prediction unit to generate path selection signals and reduce dynamic power consumption by enabling only necessary access channels, and temporarily storing branch instruction information to update the BTB during NOP periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel access of multiple cache lines is used for cache access control, then cache access speed is improved, but dynamic power consumption increases
Solution Approach 1:
The patent segments the cache access process into multiple independent channels, where each channel can be independently enabled or disabled. By dividing the parallel access structure into separable units, the system can dynamically activate only the necessary channels based on instruction type, thereby maintaining fast access when needed while reducing power consumption when full parallel access is not required.
Solution Approach 2:
The patent introduces dynamic control of cache access channels based on instruction type detection. The system transitions from static parallel access to dynamic selective access, where the number of active access channels varies according to the specific instruction being executed. This dynamic adaptation allows the system to optimize between speed and power consumption in real-time.
2Adaptability or versatility
If both jump branch instruction and non-jump branch instruction are stored in BTB entry, then branch prediction capability is improved, but conflict probability increases
Solution Approach 1:
The patent segments the branch instruction storage by creating separate storage structures or separate entry types within the BTB for jump branch instructions and non-jump branch instructions. This segmentation prevents different instruction types from conflicting for the same BTB entry, thereby reducing conflict probability while maintaining comprehensive branch prediction capability for both instruction types.
Solution Approach 2:
Instead of storing both jump and non-jump branch instructions in the same BTB entry format, the patent inverts the approach by using distinct storage mechanisms or differentiated entry structures for each instruction type. This inversion of the unified storage model eliminates conflicts arising from mixed instruction types sharing the same storage space.
Data Source
AI summary
An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information. The instruction processing apparatus selectively enables an access channel of the instruction cache based on the path prediction information by using the access control unit, to reduce dynamic power consumption in access. A corresponding path prediction method, a computer system, and a system-on-chip are also disclosed.