Path Tracing Analytics With Hardware Latency Binning
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Solution Overview
Problem
Path tracing solutions face challenges due to headers being too deep in packets for certain ASICs, leading to edit-depth limitations and incomplete timestamp access, causing performance bottlenecks and high computational costs in network controllers.
Innovation Solution
Implement optimized behavior on source nodes with edit-depth limitations and incomplete timestamp access by using CPUs and NPUs to record partial timestamps in different headers, and redefine network controller behavior to combine these for full timestamps, along with hardware-based processing at sink nodes to reduce computational load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If path tracing headers are placed deep in packets to carry 64-bit timestamps, then timestamp precision is improved, but ASIC edit-depth limitations prevent access and modification
Solution Approach 1:
The patent divides the timestamp recording function into two parts: the CPU records the upper 32 bits (seconds) in a first header, while the NPU records the lower 32 bits (nanoseconds) in a second header. This segmentation allows each component to operate within its capabilities while collectively achieving full 64-bit timestamp precision.
Solution Approach 2:
The patent introduces an intermediary mechanism where the CPU and NPU each record partial timestamp information in different headers, and the network controller later combines these partial records to reconstruct the full timestamp. This intermediary approach resolves the conflict between timestamp precision requirements and ASIC accessibility limitations.
2Loss of information
If network controller processes all path tracing analytics, then comprehensive analysis is achieved, but computational cost and performance bottlenecks increase
Solution Approach 1:
The patent extracts the analytics processing function from the network controller and implements it directly in hardware at the sink node. The sink node's NPU performs ECMP path detection, latency analysis, and other analytics locally, eliminating the need for the network controller to process every path tracing packet and significantly reducing computational overhead.
Solution Approach 2:
The sink node performs its own analytics processing independently without requiring centralized controller intervention. The hardware at the sink node autonomously detects ECMP paths, measures latency, and generates analytics, making the system self-sufficient and reducing the computational burden on the network controller.
3Device complexity
If hardware performs minimal path tracing functionality, then device complexity is reduced, but analytics capability requires software processing
Solution Approach 1:
The patent replaces software-based analytics processing with hardware-based processing at the sink node. The NPU performs analytics functions directly in hardware, substituting the traditional software processing path and enabling line-rate analytics throughput without increasing hardware complexity at other nodes.
Data Source
AI summary
Techniques for processing path tracing probe packets using hardware (e.g., hardware memory of a node) and without the involvement of a path tracing collector component of a network controller. A source node may be configured to generate and assign random flow labels to a large number of probe packets and send them through the network to a sink node. The sink node may determine whether a flow indicated by the probe packet has previously been traversed. Additionally, the sink node may determine latency values associated with the flows, and store probe packets in corresponding latency bins. The latency bins may be stored in hardware memory of the sink node. Telemetry data representing the probe packets stored in the latency bins may be sent to a network controller for further network analysis.