PathSeeker CGRA Mapping via Localized DFG Transformations

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Solution Overview

Problem

Existing modulo scheduling-based CGRA mapping techniques face challenges in efficiently mapping performance-critical loops due to their reliance on backtracking or restarting, which can lead to prolonged compilation times and suboptimal mapping quality, as they fail to effectively address mapping failures by not learning from or correcting the issues.

Innovation Solution

The PathSeeker method analyzes predecessor and successor nodes to identify mapping failures and performs localized transformations and time-slot level remapping to achieve a valid mapping, iteratively exploring different PE positions to find a solution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If backtracking or restarting is used in modulo scheduling-based CGRA mapping techniques, then mapping completeness can be achieved, but compilation time increases significantly

Engineering Contradiction:
Improvemapping completenessVSAvoidcompilation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by analyzing the Data Flow Graph (DFG) before mapping, identifying critical paths and node dependencies in advance. This preparation enables the mapping algorithm to make informed decisions without extensive backtracking, reducing compilation time while maintaining mapping completeness

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the mapping algorithm learns from previous mapping attempts and adjusts its strategy. By analyzing mapping failures and using this information to guide subsequent mapping decisions, the system avoids repetitive backtracking while ensuring complete mapping of all DFG nodes

Inventive Principle:
Principle #23Feedback

2Reliability

If backtracking is performed to resolve mapping failures, then mapping validity can be improved, but mapping quality deteriorates

Engineering Contradiction:
Improvemapping validityVSAvoidmapping quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by performing localized transformations only in the specific regions of the DFG where mapping failures occur, rather than globally backtracking. This preserves the quality of already-mapped regions while correcting local issues, maintaining overall mapping quality

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the mapping problem into independent regions based on DFG connectivity and critical paths. By handling each segment separately and applying targeted transformations, the system maintains mapping validity without compromising the quality of other segments

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If exhaustive search is performed to find optimal PE positions, then mapping quality improves, but compilation time increases

Engineering Contradiction:
Improvemapping qualityVSAvoidcompilation speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies partial action by performing exhaustive search only for critical nodes on the critical path, while using heuristic methods for non-critical nodes. This selective approach maintains high mapping quality for performance-critical operations while preserving compilation speed

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent dynamically changes search parameters based on node importance and position in the DFG. For critical nodes, it performs exhaustive search with fine-grained parameter exploration, while for non-critical nodes, it uses coarser parameter sampling, balancing quality and speed

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240311230A1Systems and methods for fast-mapping of coarse-grained reconfigurable arrays
Publication Date: 2024.09.19 THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIV OF ARIZONA
  • US20240311230A1 patent drawing
  • US20240311230A1 patent drawing
  • US20240311230A1 patent drawing

AI summary

A mapping approach (“PathSeeker”) for CGRAs analyzes mapping failures and performs local adjustments to a schedule to obtain a mapping. First, instead of backtracking or restarting the mapping as in previous mapping methods, PathSeeker analyzes the predecessor and successor nodes to find the reason behind the failed mapping. Second, PathSeeker explores local transformations for the predecessor and successor of the failed node to achieve a valid mapping. Finally, when local transformations do not yield a valid mapping, different PE positions of the other nodes in the time-slot of the failed node, the predecessor, and successor are iteratively explored, to find a valid mapping.