Patrol Read Controller for Nonvolatile Memory Power Reduction

The patent segments the patrol read operation by dividing the nonvolatile memory into multiple blocks and selectively performing read operations on only certain blocks (e.g., blocks with higher error rates or older blocks) rather than reading the entire memory area. This segmentation allows the system to maintain error detection capability while reducing the number of read operations and thus lowering power consumption.

The patent applies local quality by identifying and targeting specific blocks or regions of memory that are more prone to errors (such as blocks with higher program/erase cycle counts or blocks that have shown previous errors) for patrol read operations. By concentrating read operations on these high-risk local areas rather than uniformly reading all memory, the system achieves effective error detection with reduced power consumption.

The patent implements periodic patrol read operations with variable intervals rather than fixed frequent reads. The system adjusts the timing and frequency of patrol reads based on memory block characteristics, error rates, and usage patterns, performing reads periodically but not uniformly across all blocks. This allows the system to maintain adequate error detection accuracy while reducing overall power consumption by avoiding unnecessary frequent reads on healthy blocks.

The patent applies partial action by performing patrol read operations on only a subset of memory blocks rather than all blocks within each cycle. The system selectively targets blocks that require monitoring based on various criteria such as error history, age, or usage intensity, thereby achieving sufficient error detection accuracy with fewer read operations and reduced power consumption.