Pattern Adjusted Timing for IC Layout Verification
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Solution Overview
Problem
Current design verification processes for ICs are computationally intensive and time-consuming due to the complexity of addressing dimensional variations and manufacturing fluctuations, leading to inefficiencies in identifying and correcting problematic layout patterns that affect timing performance.
Innovation Solution
A method and apparatus for pattern-adjusted timing via multi-dimensional pattern matching, which involves scanning IC designs for problematic layout patterns, modifying netlists based on performance characteristics, and executing performance constraint analyses to generate accurate timing closures, thereby improving design validation and verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional static timing analysis methodologies are used to address parametric variability, then timing analysis can be performed, but computational complexity increases exponentially
Solution Approach 1:
The patent segments the design verification process into two distinct phases: (1) pattern recognition phase using machine learning to identify problematic layout patterns, and (2) timing analysis phase focusing only on instances containing these patterns. This segmentation reduces the computational scope from analyzing all possible variations to analyzing only relevant pattern instances, thereby reducing exponential complexity while maintaining timing analysis accuracy.
Solution Approach 2:
The patent performs preliminary pattern recognition and identification of problematic layout patterns before conducting timing analysis. By pre-identifying which layout instances contain problematic patterns using machine learning, the system prepares the analysis scope in advance, allowing timing analysis to be performed only on relevant subsets rather than all possible variations, thus reducing computational complexity.
2Reliability
If path-based statistical timing analysis is used to compute probability distribution of chip performance, then all possible sources of variation are taken into account, but computing power and memory resources are heavily consumed
Solution Approach 1:
The patent applies local quality by using machine learning to identify specific local layout patterns that are problematic, rather than analyzing all global variations. The system extracts and analyzes only the local regions containing problematic patterns, performing timing analysis selectively on these localized areas. This approach maintains reliability by focusing on critical regions while significantly reducing computing power consumption compared to analyzing all possible sources of variation.
Solution Approach 2:
The patent extracts and isolates problematic layout patterns from the overall design using machine learning techniques. By taking out only the problematic pattern instances for detailed timing analysis, rather than analyzing all possible sources of variation, the system maintains performance prediction accuracy for critical areas while reducing overall computing power and memory resource consumption.
3Productivity
If conventional design constraint definitions are used, then timing analysis can be performed, but they do not account for manufacturing fluctuations and dimensional variations
Solution Approach 1:
The patent implements feedback by using machine learning to recognize problematic layout patterns based on their correlation with manufacturing fluctuations and dimensional variations. The system learns from training data containing information about manufacturing variations and uses this knowledge to identify patterns that are likely to be problematic. This feedback mechanism enables the system to maintain fast design verification speed while accurately accounting for manufacturing precision issues through pattern recognition.
Solution Approach 2:
The patent performs preliminary training of machine learning models with data that includes manufacturing fluctuations and dimensional variations. By pre-training the system with this information, the models learn to recognize patterns that are sensitive to manufacturing variations before actual design verification begins. This preliminary action enables fast verification while maintaining accuracy in accounting for dimensional variations, as the system is pre-equipped with knowledge about manufacturing-related pattern issues.
Data Source
AI summary
An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.