Pattern-Based Clock Generation for Phase-Aligned Multi-Clock Circuits
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Solution Overview
Problem
Generating multiple phase-aligned clock signals in high-speed and complex circuits is challenging due to increased sensitivity to skew, jitter, and noise, with existing techniques either requiring sensitive analog and digital design considerations or leading to high jitter and large timing margins.
Innovation Solution
A clock signal generator system that uses a pattern selector to determine the structure of generated clock signals based on input signal patterns, ensuring phase alignment with a reference clock signal, and employs identical circuit structures for multiple clock signals, reducing skew and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock root signals are derived from a common reference clock oscillator through cascaded multiplexer circuits, then phase alignment is achieved, but signal path length increases leading to high jitter and large timing margins
Solution Approach 1:
The patent segments the clock signal generation by creating multiple independent clock root signals directly from the reference clock oscillator, rather than cascading multiplexers. Each clock root signal is generated through separate, parallel paths, reducing cumulative signal path length and jitter while maintaining phase alignment through direct derivation from the same reference source.
2Adaptability or versatility
If the number of clock root signals increases to meet complex circuit requirements, then circuit functionality is improved, but sensitivity to skew, jitter, and noise increases
Solution Approach 1:
The patent implements a universal clock generation architecture where a single reference clock oscillator serves multiple clock root signal generation functions simultaneously. This multi-functional approach allows the system to support complex circuit requirements with multiple clock signals while maintaining a common reference source that inherently reduces sensitivity to skew, jitter, and noise compared to independent clock sources.
3Reliability
If clock dividers are merged into the PLL system design to generate phase-aligned clock root signals, then phase alignment is achieved, but design complexity and verification difficulty increase
Solution Approach 1:
The patent extracts the clock division functionality from the PLL system design, allowing clock root signals to be generated independently from the reference clock oscillator. This separation simplifies the PLL design and verification while still achieving phase alignment, as the clock dividers operate as independent modules derived from the same reference source rather than being integrated into the PLL's sensitive analog and digital design.
Data Source
AI summary
An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.