Pattern-Dependent Error Correction for Fast Ethernet Receivers
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Solution Overview
Problem
Conventional Fast Ethernet receivers often fail to maintain the specified bit error rate due to issues like aged wiring, multiple segment connections, and non-ideal parameters, leading to data transmission errors such as lost start-of-stream delimiters, false idle states, and false packet ends, without additional forward error control coding.
Innovation Solution
A pattern-dependent error correction method and system for a code group alignment finite state machine (FSM) that recovers lost signals and corrects erroneous code patterns by determining specific conditions in the receiving data and error index signals, generating corrected code patterns to prevent false idle states and packet ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Fast Ethernet receiver implementation is used, then device complexity is kept simple, but reliability deteriorates due to inability to correct errors in real-world conditions
Solution Approach 1:
The patent introduces an error correction mechanism as an intermediary component between the receiver and the data stream. This mechanism includes state detection logic and pattern recognition that acts as a mediator to identify and correct errors without requiring full forward error control coding, thus improving reliability while controlling complexity
Solution Approach 2:
The patent changes the operational parameters of the receiver by implementing dynamic state tracking and pattern-dependent correction logic. Instead of using fixed conventional reception parameters, the system adapts parameters based on detected error patterns and state transitions, allowing error correction in real-world conditions without full ECC complexity
2Reliability
If no additional forward error control coding is used, then device complexity is reduced, but reliability deteriorates due to inability to assure specified BER in real conditions
Solution Approach 1:
The patent extracts and implements only the essential error correction functionality needed for pattern-dependent errors, rather than implementing complete forward error control coding. This selective extraction provides necessary reliability improvement while avoiding the complexity overhead of full ECC schemes
Solution Approach 2:
The patent applies partial error correction action by implementing correction logic for specific detectable error patterns rather than comprehensive correction for all possible errors. This partial action approach achieves practical reliability improvement without the complexity of exhaustive error control
3Reliability
If error correction mechanism is implemented, then reliability is improved by correcting multi-bit errors, but device complexity increases due to additional correction logic
Solution Approach 1:
The patent segments the error correction function into distinct state machines and pattern recognition modules. By dividing the correction logic into manageable segments that handle specific error types and states separately, the system achieves improved reliability while keeping each segment's complexity controlled and manageable
Data Source
AI summary
A pattern-dependent error correction method and system for a code group alignment finite state machine (FSM) are disclosed. A state corrector generates a start-of-stream delimiter (SSD) detected signal to the FSM when the FSM is in an idle state and at least one condition due to a lost SSD signal is met; and the state corrector generates an idle detected signal to the FSM when at least one condition due to a lost idle signal is met. A pattern corrector generates a corrected code pattern {J,K} to FSM when the FSM is in an idle state and at least one condition due to a false idle state is met; and the pattern corrector generates a corrected code pattern {T,R} to the FSM when the FSM is in a data state, a start of stream state or a data error state, and at least one condition due to a false packet end is met.