Pattern Detector Circuit for Concurrent DSP Arithmetic
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Solution Overview
Problem
The increasing demand for real-time, concurrent arithmetic operations in digital signal processing applications, such as in 3G base stations, is not adequately met by traditional DSP chips or Programmable Logic Devices (PLDs) due to bottlenecks in the PLD fabric, necessitating a more efficient solution for pattern detection and arithmetic processing.
Innovation Solution
An integrated circuit (IC) with a pattern detection circuit that includes an arithmetic logic unit (ALU) programmed by an opcode, a comparison circuit with multiplexers for selecting patterns and masks, and a masking circuit for bitwise operations, integrated within a programmable logic and interconnect structure to enhance DSP performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP elements are configured in programmable logic to allow concurrent DSP operations, then the quantity of arithmetic operations increases, but the PLD fabric becomes a bottleneck limiting further performance improvement
Solution Approach 1:
The patent divides the DSP processing function into separate dedicated elements: arithmetic logic units for computation and pattern detector circuits for pattern recognition. This segmentation allows each element to be optimized independently, with the pattern detector operating in parallel with the arithmetic units, thereby increasing concurrent operations without overloading the interconnect fabric.
Solution Approach 2:
The patent introduces dedicated pattern detector circuits as intermediary components that receive inputs directly from registers and produce outputs directly to registers, bypassing the need for complex fabric routing. This intermediary structure eliminates the fabric bottleneck by providing direct dedicated pathways for pattern detection operations.
2Speed
If dedicated pattern detector circuits are integrated with arithmetic logic units, then real-time processing capability improves, but device complexity increases
Solution Approach 1:
The patent merges the pattern detector circuit with the arithmetic logic unit by sharing common components such as registers, multiplexers, and interconnect structures. This integration allows both arithmetic operations and pattern detection to occur within a unified circuit structure, improving real-time processing capability while minimizing the increase in overall device complexity through resource sharing.
Data Source
AI summary
An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.