Pattern-Filtered Clock Adjustment for Single-Phase SerDes CDR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Baud-rate CDR in high-speed SerDes receivers suffers from multiple lock phase issues due to decision errors caused by intersymbol interference, leading to incorrect phase error detection and timing recovery problems.
Innovation Solution
A clock adjustment circuit employing a pattern filter circuit to select predetermined data patterns for phase error detection in acquisition and tracking modes, using a phase error detector and calculation circuit to determine timing compensation, ensuring single lock phases and improved timing recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Baud-rate CDR is used for low power consumption, then power consumption is reduced, but multiple lock phase issues occur leading to decision errors
Solution Approach 1:
The patent applies preliminary action by pre-selecting specific data patterns (acquisition patterns and tracking patterns) before phase error detection. The pattern filter circuit预先 filters incoming data to identify suitable patterns that guarantee correct lock phase, thereby preventing decision errors before they occur while maintaining low power consumption of Baud-rate CDR
Solution Approach 2:
The patent changes the parameter of data pattern selection by switching between different predetermined patterns based on operating mode (acquisition mode using acquisition patterns, tracking mode using tracking patterns). This parameter change ensures that only patterns with known good lock phase characteristics are used for phase error detection, resolving the multiple lock phase issue
2Reliability
If Bang-bang CDR is used to avoid multiple lock phase issues, then decision accuracy is improved, but power consumption increases
Solution Approach 1:
The patent introduces an intermediary mechanism - the pattern filter circuit and predetermined data patterns - that mediates between the low-power Baud-rate CDR and the requirement for accurate phase error detection. This intermediary selects only suitable patterns for detection, enabling Baud-rate CDR to achieve both low power consumption and high decision accuracy without needing Bang-bang CDR
3Speed
If all consecutive data samples are used for phase error detection, then detection speed is improved, but decision errors increase due to intersymbol interference
Solution Approach 1:
The patent extracts only the useful subset of data samples by using the pattern filter circuit to identify and select predetermined acquisition patterns and tracking patterns from the stream of consecutive data samples. This extraction eliminates samples suffering from intersymbol interference while maintaining detection speed by focusing computational resources only on validated patterns
Data Source
AI summary
A clock adjustment circuit includes a pattern filter circuit, a phase error detector (PED) circuit, and a phase error calculation circuit. The pattern filter circuit selects first predetermined data patterns from a plurality of consecutive data samples under an acquisition mode of the clock adjustment circuit, wherein the plurality of consecutive data samples are derived from an output of a first sampler circuit. The PED circuit detects phase errors according to an output of the pattern filter circuit and error samples derived from an output of a second sampler circuit. The phase error calculation circuit determines timing compensation of a sampling clock according to an output of the PED circuit, wherein the sampling clock is used by the first sampler circuit and the second sampler circuit.