Pattern Generator Address Operation Circuit for DRAM Testing
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Solution Overview
Problem
The complexity of programming in memory test apparatuses for multi-bank DRAM configurations is increased due to the need for generating and managing row addresses, especially when burst operations require different addresses, leading to inefficient operations and user burden.
Innovation Solution
A pattern generator with an address operation circuit and row address memory that uses a memory control signal as both a save and load address, eliminating the need for explicit address generation for the row address memory, and includes an output holding circuit to manage burst lengths, simplifying programming by reducing the need for repetitive load commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If an address save/load circuit is employed to save row addresses in row address memory, then the same row address can be reused without regeneration, but the programming complexity increases due to the need to generate separate load addresses
Solution Approach 1:
The bank address signal is made to serve dual purposes: it identifies the target bank for memory access and simultaneously serves as the address signal for the row address memory. This multi-functionality eliminates the need for separate address generation logic, reducing programming complexity while maintaining the time-saving benefits of address reuse
Solution Approach 2:
The invention merges the bank address function with the row address memory address function into a single signal. Instead of having separate signals for bank selection and for accessing the row address memory, both functions are combined into the bank address signal, simplifying the overall control logic
2Measurement precision
If separate address generation is implemented for row address memory access, then precise address control is achieved, but the programming becomes more complicated and burdensome
Solution Approach 1:
The bank address signal performs multiple functions simultaneously: it selects the target bank, identifies the row address to be saved, and provides the address for loading/saving row addresses in the row address memory. This eliminates the need for separate address generation while maintaining precise control
3Measurement precision
If row addresses are regenerated for each bank access, then address accuracy is maintained, but operational efficiency decreases due to redundant generation
Solution Approach 1:
Row addresses are saved in the row address memory during initial bank accesses. When the same bank is accessed again, the pre-saved row address is quickly loaded from memory rather than being regenerated, significantly improving operational efficiency while maintaining address accuracy
Solution Approach 2:
Instead of regenerating row addresses, the system recovers and reuses previously generated addresses by storing them in the row address memory. This recovery mechanism eliminates redundant generation operations while ensuring address accuracy is maintained
Data Source
AI summary
An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory.