Pattern Matcher and FPGA Replication for Ultra-Low Latency Data Paths
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Solution Overview
Problem
Existing data communication systems face challenges in reducing latency during high-speed data pattern matching operations, often requiring complex processing that increases latency and response times.
Innovation Solution
A system and method that utilize a data processing device with a replicator to replicate ingress data and send it to both a pattern matcher and a field programmable gate array (FPGA), allowing the FPGA to perform bit operations based on a trigger signal generated by the pattern matcher, while a line rate descrambler removes header data without a gearbox, reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If complex data processing operations are performed to reduce latency, then latency is reduced, but device complexity increases
Solution Approach 1:
The system segments data processing into two distinct paths: a low-latency path using FPGA for time-critical bit operations and pattern matching, and a higher-latency path using software for complex processing tasks. This segmentation allows each component to be optimized for its specific function, reducing overall system latency without requiring all components to be overly complex.
Solution Approach 2:
The patent introduces a replicator as an intermediary component that receives ingress data and creates multiple copies simultaneously routed to different processing paths (FPGA and software). This intermediary enables parallel processing without requiring direct complex interactions between the processing units, simplifying the overall system architecture while achieving low latency.
2Speed
If simple bit operations are performed outside FPGA, then processing speed increases, but device complexity increases
Solution Approach 1:
The system merges hardware (FPGA) and software processing into a unified data processing architecture. Simple bit operations are performed in hardware at line rate, while more complex operations are handled by software. The replicator and pattern matcher coordinate these two processing modes, achieving high speed processing without requiring all operations to be implemented in complex hardware.
3Loss of time
If header data is removed without a gearbox, then latency is reduced, but processing precision may be affected
Solution Approach 1:
The line rate descrambler performs preliminary processing of the data stream by removing header data before the main processing stages. This preliminary action eliminates unnecessary data early in the processing pipeline, reducing latency for subsequent operations while maintaining data integrity through coordinated processing between the descrambler, replicator, and pattern matcher.
Data Source
AI summary
In one or more implementations, a data processing device and a data processing method are disclosed that includes a data communication port configured to transmit and receive data to and from at least one computing device. Further, a replicator is included that is configured to replicate ingress data received from the data communication port to a pattern matcher and a field programmable gate array. The pattern matcher is configured to receive the replicated data directly from the replicator and to generate and transmit a trigger signal to the field programmable gate array. Still further, the field programmable gate array is configured to receive the replicated data from the replicator and the trigger signal from the pattern matcher and to perform bit operations on the replicated data as a function of the trigger signal.