Pattern-Matching IC for Compact Hardware Error Correction
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Solution Overview
Problem
Existing hardware implementations for error detection and correction in security-related integrated circuits, such as those used in smart cards and automotive control processors, face challenges in efficiently detecting and correcting bit errors, especially in RRAM memory, due to the large number of error cases that require complex calculations and large table sizes, making it difficult to implement efficiently in hardware.
Innovation Solution
The integration of a pattern matching circuit, selection circuit, and output circuit in an integrated circuit that uses pre-calculated function values stored in tables, leveraging properties like invariance or invertibility under transformations, such as the Frobenius endomorphism, to reduce the number of stored function values and implement error detection and correction efficiently in hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware implementations use large tables to store all error correction function values, then error detection and correction capability is improved, but chip surface area increases significantly
Solution Approach 1:
The patent segments the error correction function into multiple components: a pattern matching circuit that identifies error patterns, a transformation application unit that applies Frobenius endomorphism transformations, and a smaller table that stores only representative function values. This segmentation allows the system to avoid storing complete error correction tables for all possible error cases, thereby reducing chip surface area while maintaining full error detection and correction capability.
Solution Approach 2:
The patent applies transformations (Frobenius endomorphism) to the input error patterns in advance to generate equivalent representative patterns before table lookup. This preliminary transformation action allows the system to map multiple different error patterns to a smaller set of representatives, reducing the table size needed while ensuring all error cases can be corrected.
2Measurement precision
If hardware implementations use complex calculation circuits to handle all error cases, then error correction accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces transformation functions (Frobenius endomorphism) as intermediaries between the input error patterns and the correction tables. These transformations serve as mediators that convert arbitrary error patterns into representative forms that can be efficiently looked up in smaller tables, maintaining correction accuracy while reducing circuit complexity compared to implementing full error correction logic for all cases.
Solution Approach 2:
The patent changes the parameter representation of error patterns by applying field transformations (Frobenius endomorphism) that map error patterns to equivalent representatives. This parameter transformation allows the system to work with a reduced set of representative error cases rather than all possible error patterns, simplifying the hardware implementation while preserving correction accuracy.
3Adaptability or versatility
If software implementations are used for error correction, then flexibility is improved, but execution speed decreases
Solution Approach 1:
The patent replaces the mechanical/software-based error correction approach with a hardware-circuit implementation. The pattern matching circuit, transformation application unit, and table lookup mechanism are implemented as dedicated hardware circuits that operate in parallel, providing both the flexibility of programmable error correction and the high speed of hardware execution, eliminating the speed penalty associated with software implementations.
Data Source
AI summary
An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.