Pattern Matching Optical Proximity Correction for Semiconductor Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current optical proximity correction (OPC) processes are hindered by slow computation speeds and consistency issues, particularly in designs with regular arrays of identical features, due to large storage requirements and algorithm inconsistencies.
Innovation Solution
The implementation of pattern matching techniques to identify and partition regular arrays of identical layout patterns into core and boundary portions, applying OPC process information specifically to the core portions to enhance speed and consistency, while performing conventional OPC on boundary portions and other regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional OPC processes are applied to designs with regular arrays of identical features, then manufacturing precision is maintained, but computation time increases significantly and consistency issues arise
Solution Approach 1:
The patent segments the layout design into distinct regions: regular array regions (with identical repeating features) and non-regular regions (with unique or varied features). This segmentation allows different OPC strategies to be applied to each region type, enabling faster processing of regular arrays while maintaining precision for both region types.
Solution Approach 2:
The patent creates a reference pattern from a single representative cell of the regular array and generates OPC corrections for this reference pattern. This reference pattern is then copied and applied to all identical cells in the regular array, eliminating the need to perform separate OPC calculations for each individual cell while maintaining manufacturing precision.
2Manufacturing precision
If conventional OPC processes are applied to regular arrays, then pattern fidelity is maintained, but algorithm inconsistencies occur across identical features
Solution Approach 1:
The patent develops a universal OPC correction set that serves all identical cells in a regular array. By creating a single reference pattern correction that can be universally applied to all matching cells, the patent ensures consistent pattern fidelity across the entire array while reducing computational overhead.
Solution Approach 2:
The patent copies the OPC corrections derived from the reference pattern to all identical cells in the regular array. This copying mechanism ensures that all identical features receive exactly the same corrections, eliminating algorithm inconsistencies and improving reliability across the design.
3Manufacturing precision
If full OPC processing is applied to all regions, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The patent divides the layout into regular array regions and non-regular regions, applying optimized processing to regular arrays and conventional processing to non-regular regions. This segmentation improves overall productivity by reducing redundant calculations in regular areas while maintaining OPC accuracy through the reference pattern approach.
Solution Approach 2:
The patent applies partial OPC processing to regular array regions by using reference patterns, performing fewer calculations than full OPC would require. This partial action approach maintains sufficient manufacturing precision for regular features while significantly improving productivity compared to applying full OPC to all regions.
Data Source
AI summary
Aspects of the invention relate to techniques for improving speed and consistency of OPC processes based on pattern matching. Pattern matching may be performed on a layout design to determine one or more arrays in the layout design that comprise arrays of identical layout patterns of which each matches a reference pattern. The one or more arrays may then be partitioned into core portions and boundary portions. The OPC process information for the reference pattern may be applied to the core portions, while a conventional OPC process may be performed on the boundary portions and layout regions outside of the one or more arrays.