Pattern-Enabled Memory Circuit for Single-Cycle Bit Access

Solution Overview

Problem

Conventional memory elements in digital circuits often cannot access or write a large pattern of bits in a single clock cycle, leading to inefficiencies in data storage and retrieval, and adding access ports increases the memory's area and power footprint.

Innovation Solution

A digital circuit configuration comprising a target memory, pattern memory, pattern-enable array, and multiplexer, which allows for associating a pattern with the target memory, enabling access and writing of a pattern of bits in a single clock cycle without significantly increasing complexity or cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If access ports are added to increase memory access capability, then the number of concurrent accesses is improved, but the memory area and power footprint significantly increase

Engineering Contradiction:

Improvenumber of concurrent accessesVSAvoidmemory area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The memory access system is segmented into multiple access ports, each handling a portion of the memory space. This allows concurrent accesses to different memory segments simultaneously, improving productivity without requiring a single large port that would increase area and power consumption proportionally.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of memory addressing by adding port identification bits to the address bus. This allows the same physical memory location to be accessed through multiple virtual ports, effectively increasing concurrent access capability without proportionally increasing the physical memory area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If access ports are added to increase memory access capability, then the number of concurrent accesses is improved, but the power footprint significantly increases

Engineering Contradiction:

Improvenumber of concurrent accessesVSAvoidpower footprint

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The memory access system is segmented into multiple access ports, each handling a portion of the memory space. This allows concurrent accesses to different memory segments simultaneously, improving productivity without requiring a single large port that would increase area and power consumption proportionally.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of memory addressing by adding port identification bits to the address bus. This allows the same physical memory location to be accessed through multiple virtual ports, effectively increasing concurrent access capability without proportionally increasing the physical memory area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Device complexity

If conventional memory elements are used, then the memory structure is simple, but accessing or writing a large pattern of bits in a single clock cycle is not possible

Engineering Contradiction:

Improvememory structure complexityVSAvoidaccess speed for large patterns

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent prepares the memory system in advance by setting up port-specific control signals and address routing before the actual access operation. This preliminary configuration enables the memory to handle large pattern transfers in a single clock cycle by having all necessary access paths pre-established.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The memory system dynamically configures its access behavior based on the port identification bits in the address. Different ports can be activated simultaneously for different memory segments, allowing the system to adapt its access pattern dynamically to handle large data transfers in a single clock cycle.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP4668272A1Digital circuit and method of operation in a digital circuit

Publication Date: 2025.12.24 SEMIDYNAMICS TECHNOLOGY SERVICES SL

Figure 1
Figure 2
Figure 3~4

AI summary

A digital circuit (1) comprising a target memory (2), a pattern memory (3), a pattern-enable array (4) and a multiplexer (5), wherein the target memory (2) is configured to store entries and output a respective output (TMout); the pattern memory (3) is configured to store a pattern and to output a respective output (PMout); the pattern-enable array (4) comprises memory elements (6) each of which is associated with a respective address of a corresponding one of the entries and is configured to be set to a state indicative of whether the respective address is associated with the stored pattern or not; the multiplexer (5) is configured to select between the received respective output (TMout) of the target memory (2) and the received respective output (PMout) of the pattern memory (3) using the output (PEAout) of the pattern-enable array (4) for enabling the selection. Also, a method.