Semiconductor Pattern Openings for Concave-Corner Fidelity

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Solution Overview

Problem

Pattern corner rounding during photolithography and etching processes in semiconductor manufacturing leads to reduced design margins and compromised pattern fidelity, particularly affecting critical dimension control in smaller process nodes.

Innovation Solution

A method involving directional etching techniques is employed to transform target patterns with concave corners into hole-type patterns free of concave corners, followed by expanding these openings to maintain design margins and enhance pattern fidelity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithography and etching processes are used, then manufacturing process simplicity is maintained, but pattern corner rounding occurs leading to reduced pattern fidelity

Engineering Contradiction:
Improvepattern fidelityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the pattern formation process into multiple stages: forming initial openings with rounded corners, then applying directional etching to selectively sharpen corners. This segmentation allows each stage to address specific aspects of pattern fidelity without overwhelming complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary action by first forming openings with rounded corners through conventional photolithography, then preparing the structure for directional etching. This preliminary formation simplifies the subsequent directional etching step while ensuring final pattern fidelity

Inventive Principle:
Principle #10Preliminary action

2Productivity

If process scaling is continued to increase functional density, then production efficiency and cost reduction are achieved, but pattern corner rounding becomes more prominent affecting critical dimension control

Engineering Contradiction:
Improveproduction efficiencyVSAvoidcritical dimension control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the etching parameters by introducing directional etching with specific angle control. This parameter change allows precise control over corner sharpness while maintaining the overall scaling benefits for production efficiency

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies dynamic control in the directional etching process where etching conditions can be adjusted during processing to optimize both corner sharpness and production throughput, allowing flexibility in managing the trade-off between precision and efficiency

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively maintains design margins and improves pattern fidelity by ensuring that openings are free of concave corners, thereby enhancing the precision of semiconductor manufacturing processes.

Implementation Method 1

applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening

Methodology Applied
Scientific EffectDirectional etching:

Data Source

PatentUS20250308892A1Pattern fidelity enhancement
Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250308892A1 patent drawing
  • US20250308892A1 patent drawing
  • US20250308892A1 patent drawing

AI summary

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate, the substrate having a plurality of features to be processed, forming a patterning layer over the substrate, forming a plurality of openings in the patterning layer, the plurality of openings being free of concave corners and partially overlapping with the plurality of features in a top view, expanding each of the plurality of openings in the patterning layer, resulting in a plurality of expanded openings in the patterning layer, the plurality of expanded openings fully overlapping with the plurality of features in the top view, and performing an etching process or an ion implantation process to the plurality of features through the plurality of expanded openings.