Pattern Match Prefetcher Using PC-Based Learning for Varying Offsets
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Solution Overview
Problem
Existing prefetching techniques in processors face challenges in accurately predicting memory access patterns, leading to inefficiencies in cache usage, increased power consumption, and circuit area utilization, particularly when dealing with varying starting addresses and offsets in memory access patterns.
Innovation Solution
Implementing a Bayesian pattern engine (BPE) that uses program counters for long-term learning, combined with compressed map storage and adaptive prefetch constraint adjustment, to enhance prefetch accuracy and efficiency across multiple cache levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional prefetching techniques are used, then cache hit rate may be improved, but prefetch accuracy deteriorates due to inability to handle varying starting addresses and offsets
Solution Approach 1:
The patent changes the parameter representation by using program counter (PC) relative addressing instead of absolute addresses. The PC-based offset is calculated as (accessed_address - PC), allowing the same access pattern to be recognized regardless of the starting address. This parameter transformation enables the prefetcher to adapt to varying starting addresses while maintaining high prefetch accuracy through pattern matching.
2Loss of time
If aggressive prefetching is performed, then memory latency is reduced, but power consumption increases
Solution Approach 1:
The patent implements feedback mechanisms through quality factors (Q-factors) that track prefetch accuracy and cache hit rates. The system monitors whether prefetched data is actually used and adjusts prefetch aggressiveness accordingly. When prefetch accuracy drops or cache hits decrease, the system reduces prefetching activity, thereby lowering power consumption while maintaining optimal memory latency performance.
Solution Approach 2:
The prefetching system dynamically adjusts its behavior based on runtime conditions. The quality factors and confidence levels are continuously updated, allowing the prefetcher to transition between aggressive and conservative modes. This dynamic adaptation ensures that power consumption is optimized while still achieving low memory latency when prefetching is beneficial.
3Measurement precision
If prefetch control circuitry is expanded to improve prefetch accuracy, then prefetch coverage increases, but circuit area increases
Solution Approach 1:
The patent makes the access map data structure universal by using PC-relative offsets instead of absolute addresses. The same access map structure and pattern matching logic can handle any starting address and offset combination, eliminating the need for multiple specialized data structures or tables. This universality achieves high prefetch coverage without proportionally increasing circuit area.
Solution Approach 2:
Instead of storing complete absolute address patterns, the system stores compact PC-relative offset patterns. When a pattern is matched, the actual prefetch addresses are generated by adding the PC-relative offset to the current PC value. This copying approach generates the full address space from a compact template, achieving high coverage with minimal storage area.
4Productivity
If pattern matching prefetching is used, then spatial locality is exploited, but handling of varying offsets becomes difficult
Solution Approach 1:
The patent transforms the offset parameter from absolute to PC-relative form. By storing offsets as (accessed_address - PC), the system maintains the spatial locality information needed for pattern matching while automatically adapting to varying starting addresses. The PC-relative representation preserves the relative spacing between memory accesses, enabling effective spatial locality exploitation regardless of the absolute address or offset values.
Data Source
AI summary
Disclosed techniques relate to supplemental PC-based learning for a pattern-based prefetcher. In some embodiments, prefetch circuitry is configured to store access map data based on address information corresponding to memory accesses and generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache. In some embodiments, supplemental access tracking circuitry is configured to store initial access tracking information for offsets corresponding to a first access map evicted from the prefetch circuitry, store program counter information associated with an initial memory access that touched the first access map, update the access tracking information, based on one or more additional access maps evicted from the prefetch circuitry that match the stored program counter information, and generate, in response to a hit and based on the updated access tracking information, a starting access map for allocation in the prefetch circuitry.