Pattern-Recognition Bus for CPU Data Stream Processing
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Solution Overview
Problem
The increasing complexity of pattern recognition tasks in computing is hindered by the lack of a widely accepted communication protocol between dedicated pattern-recognition hardware and central processing units, leading to implementation challenges and bottlenecks in data stream processing.
Innovation Solution
A pattern-recognition bus is introduced, similar or identical to a memory bus, to facilitate communication between pattern-recognition processors and CPUs, leveraging existing knowledge of memory bus protocols and reducing the need for additional signals, thus simplifying the implementation of pattern-recognition hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated pattern-recognition hardware is implemented, then pattern recognition speed is improved, but communication protocol complexity increases
Solution Approach 1:
The patent applies universality by making the pattern-recognition bus identical to or similar to the memory bus, allowing the same physical infrastructure to serve multiple functions (memory access and pattern recognition). This eliminates the need for designers to learn entirely new communication protocols, as they can leverage their existing knowledge of memory bus protocols while achieving dedicated pattern recognition hardware acceleration.
2Device complexity
If multiple patterns are searched sequentially, then implementation complexity is reduced, but processing speed deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the pattern recognition task into parallel operations. Instead of searching for multiple patterns sequentially, the system uses multiple recognition modules that can search for different patterns simultaneously on the same data stream. This parallel segmentation maintains relatively simple implementation while dramatically improving processing speed.
3Adaptability or versatility
If new communication protocols are learned, then pattern-recognition hardware capability is improved, but implementation cost increases
Solution Approach 1:
The patent applies self-service by allowing the system to leverage existing knowledge and infrastructure. Designers can use their existing expertise with memory bus protocols to implement pattern-recognition hardware, eliminating the need to invest time and resources in learning entirely new communication protocols. The pattern-recognition bus serves itself by being compatible with established protocols.
4Measurement precision
If data stream search delay increases, then pattern matching accuracy is improved, but system throughput deteriorates
Solution Approach 1:
The patent applies continuity of useful action by enabling parallel pattern recognition operations that process the data stream continuously without sequential delays. Multiple recognition modules operate simultaneously on the same data stream, maintaining continuous processing throughput while performing comprehensive pattern matching checks, thus avoiding delays that would compromise system throughput.
Data Source
AI summary
Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.