Pattern Recognition Processor Power Control Circuit
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Solution Overview
Problem
Pattern recognition processors face high power consumption due to the need to search large data streams for multiple patterns simultaneously, leading to increased memory access and processing delays.
Innovation Solution
The implementation of a pattern-recognition processor that uses parallel finite state machines and a power control circuit to selectively activate and deactivate blocks based on search criteria, reducing unnecessary memory access and power usage by deactivating inactive blocks during processing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory core is accessed during each processing cycle to search for multiple patterns, then pattern recognition completeness is improved, but power consumption increases
Solution Approach 1:
The patent divides the memory core into multiple blocks that can be independently activated. Instead of accessing all memory blocks simultaneously, the system selectively activates only those blocks containing patterns relevant to the current data stream being searched, thereby reducing power consumption while maintaining complete pattern recognition capability.
Solution Approach 2:
The patent implements dynamic block activation where memory blocks are activated or deactivated based on the specific search criteria and data stream being processed. This dynamic adjustment allows the system to adapt power consumption to actual processing needs, ensuring complete pattern recognition only when necessary while saving power during idle or low-activity periods.
2Use of energy by moving object
If sequential searching is used for each pattern in a data stream, then power consumption is reduced, but processing delay increases
Solution Approach 1:
The patent segments the pattern search process into parallel operations by dividing patterns into different blocks that can be searched simultaneously. Multiple pattern searches are conducted in parallel across different memory blocks, reducing overall processing delay while maintaining lower power consumption compared to full memory access.
Solution Approach 2:
The patent applies partial action by activating only the necessary subset of memory blocks required for the current search task rather than accessing the entire memory core. This selective activation reduces power consumption while maintaining adequate processing speed by focusing computational resources on relevant patterns only.
3Adaptability or versatility
If the number of patterns to search increases, then pattern recognition capability is improved, but processing speed decreases
Solution Approach 1:
The patent organizes patterns into multiple segmented blocks within the memory core, allowing the system to handle a large total number of patterns by distributing them across blocks. This segmentation enables selective activation of only those blocks containing relevant patterns, maintaining processing speed despite increased overall pattern recognition capability.
Solution Approach 2:
The patent creates a universal memory block structure where each block can store different pattern types and be activated for different search criteria. This multi-functional design allows the system to efficiently handle diverse pattern recognition tasks with varying numbers of patterns, maintaining processing speed through selective block activation rather than being constrained by the total pattern count.
Data Source
AI summary
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.