Pattern-Recognition Processor With Self-Selecting Bus Decoder
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Solution Overview
Problem
Existing microcontrollers face challenges in adding pattern recognition functionality due to space, power, and cost constraints, leading to inefficiencies in data processing and increased delays in identifying patterns within data streams.
Innovation Solution
A pattern-recognition processor is integrated as a peripheral device or enhanced via software/firmware/hardware with a self-selecting bus decoder, allowing it to operate in parallel with microcontrollers, reducing the need for additional components and enabling efficient pattern recognition without increasing microcontroller costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional functions (memory, bus translation) are added to microcontrollers, then functionality is improved, but device complexity and cost increase
Solution Approach 1:
The system is divided into separate functional modules: the microcontroller handles core processing while pattern recognition functionality is implemented as a separate peripheral device. This segmentation allows each component to be optimized independently and reduces the complexity burden on the microcontroller.
Solution Approach 2:
A dedicated peripheral device with its own bus decoder acts as an intermediary between the microcontroller and the pattern recognition engine. This intermediary handles the complex bus translation and address decoding tasks, freeing the microcontroller from these burdens.
2Productivity
If pattern recognition hardware is implemented, then pattern recognition capability is improved, but device complexity and cost increase
Solution Approach 1:
The pattern recognition functionality is extracted from the microcontroller and implemented as a separate peripheral device. This extraction allows the microcontroller to remain simple while gaining access to sophisticated pattern recognition capabilities through the dedicated hardware module.
Solution Approach 2:
The peripheral device includes its own self-contained bus decoder that automatically handles address decoding and bus translation without requiring microcontroller intervention. This self-service capability reduces the overall system complexity by eliminating the need for microcontroller-based bus translation.
3Measurement precision
If multiple patterns are searched sequentially, then pattern recognition accuracy is improved, but processing time increases
Solution Approach 1:
Multiple search patterns are prepared and loaded into the pattern recognition peripheral in advance. The peripheral maintains a queue of patterns ready for immediate processing, eliminating delays associated with loading patterns during data stream analysis.
Solution Approach 2:
The pattern recognition peripheral operates continuously on incoming data streams, maintaining parallel processing of multiple patterns without interruption. This continuous operation eliminates the sequential processing delays that would occur if patterns were searched one at a time.
Data Source
AI summary
Disclosed are devices and methods, among which is a pattern-recognition processor coupled to a microcontroller. The pattern-recognition processor may act as a peripheral device to the microcontroller and provide supplemental pattern recognition functionality to the existing functionality of the microcontroller.