Semiconductor Pattern Segmentation for Active Edge Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor manufacturing processes damage the ends of active regions during the etching process, especially as design dimensions decrease, leading to performance issues in dynamic random access memory (DRAM) devices.

Innovation Solution

A method involving the formation of a substrate with first trenches and a pattern, followed by a dielectric layer covering the sidewalls, and subsequent segmentation to form a second pattern, which protects the edges from damage during the etching process by using a protective dielectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the critical dimensions are reduced to increase storage density, then the storage capacity is improved, but the active region edges become more susceptible to damage during etching

Engineering Contradiction:
Improvestorage capacityVSAvoidedge integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

A protective dielectric layer is formed over the active region edges before the etching process. This preliminary protective action prevents damage to the edges during subsequent etching operations, allowing for reduced critical dimensions while maintaining edge integrity and device reliability.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If the active area size is reduced to increase device density, then the device integration is improved, but the manufacturing precision requirements become more stringent

Engineering Contradiction:
Improveactive areaVSAvoidetching precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The protective dielectric layer acts as an intermediary between the etching process and the active region edges. It serves as a buffer that protects the edges from direct etching damage, thereby reducing the stringency of manufacturing precision requirements while enabling smaller active area dimensions for higher device density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If the critical dimensions are reduced to improve storage density, then the storage density is improved, but the performance reliability deteriorates due to edge damage

Engineering Contradiction:
Improvestorage densityVSAvoidperformance reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The protective dielectric layer is applied in advance to shield active region edges from etching-induced damage. This preliminary protection maintains performance reliability even when critical dimensions are reduced to achieve higher storage density, effectively resolving the contradiction between density improvement and reliability maintenance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12009250B2Semiconductor device and a method making the same
Publication Date: 2024.06.11 CHANGXIN MEMORY TECH INC
  • US12009250B2 patent drawing
  • US12009250B2 patent drawing
  • US12009250B2 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate includes a plurality of first trenches and a first pattern having an array of lines each formed between adjacent two of the plurality of first trenches; forming a first dielectric layer to cover at least the sidewalls of each of the lines in the array of the first pattern; and each of the lines in the array of the first pattern is segmented to form elements of a second pattern.