Pattern Shape Determination for Semiconductor OPC Verification
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Solution Overview
Problem
In semiconductor manufacturing, the scaling of integrated circuit patterns poses challenges in maintaining dimensional accuracy during lithography and etching processes, leading to inefficiencies in pattern formation, particularly due to the time-consuming nature of OPC verification processes which require simulating identical patterns for verification.
Innovation Solution
A pattern shape determining method that sets reference positions on patterns to assess dimensional differences within allowable tolerances, allowing for efficient and accurate identification of identical patterns by considering distance from a point of interest, thereby streamlining the verification process and reducing the need for full-scale OPC verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-scale OPC verification is performed on the whole integrated circuit pattern, then verification accuracy is improved, but verification time increases significantly
Solution Approach 1:
The patent divides the integrated circuit pattern into multiple identical pattern units and selects only one representative unit for verification. By segmenting the verification scope from the entire pattern to a single representative pattern, the verification time is significantly reduced while maintaining verification accuracy, as the representative pattern captures the essential verification requirements.
Solution Approach 2:
The patent uses a representative pattern that is identical to multiple other patterns in the integrated circuit pattern. By verifying only this representative pattern, the verification results can be applied to all identical patterns through copying the verification outcome, thereby reducing verification time without sacrificing accuracy.
2Reliability
If identical patterns are extracted and full simulation is performed on each, then verification completeness is improved, but processing efficiency deteriorates
Solution Approach 1:
The patent merges the verification of multiple identical patterns into a single verification process. By recognizing that multiple patterns are identical and performing verification only on one representative pattern, the processing efficiency is improved while verification completeness is maintained through the representative pattern's ability to represent all identical patterns.
Solution Approach 2:
The representative pattern serves multiple functions: it represents itself, and it also represents all other identical patterns in the integrated circuit pattern. This multi-functionality allows a single verification process to cover multiple patterns, improving processing efficiency while maintaining verification completeness.
Data Source
AI summary
According to the pattern shape determining method of the embodiment, a first reference position of a pattern shape is set on a first pattern and a second reference position of a pattern shape is set on a second pattern. Moreover, an allowable dimensional difference between the first pattern and the second pattern is set to a value corresponding to a distance from the first reference position. Then, it is determined whether the second pattern has a pattern shape identical with the first pattern, based on whether a dimensional difference between the first pattern and the second pattern is within a range of an allowable dimensional difference set at a position at which the dimensional difference is calculated.