Patterned Adhesive Via Formation for 3D IC Bonding
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Solution Overview
Problem
The fabrication of three-dimensional integrated circuit devices requires additional manufacturing steps to join semiconductor wafers, increasing costs and the risk of defects, which reduces the yield of these devices.
Innovation Solution
Semiconductor devices are fabricated by bonding semiconductor wafers together using a patterned adhesive material, such as benzocyclobutene, allowing for lateral expansion during bonding and forming through-substrate vias to provide electrical interconnection between the wafers, thereby reducing the number of manufacturing steps and potential defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to join semiconductor wafers, then the devices can be integrated vertically, but the number of manufacturing steps increases and the risk of defects increases, reducing yield
Solution Approach 1:
The patent combines multiple manufacturing operations into a single integrated process. Specifically, the adhesive material is patterned on the first substrate, and then both the adhesive material and vias are formed simultaneously in one bonding step rather than separate steps. This merging of operations reduces the total number of manufacturing steps and minimizes the risk of defects between separate processing stages.
Solution Approach 2:
The adhesive material is patterned on the first substrate before the bonding process. This preliminary patterning allows the adhesive to be in place and ready when the substrates are bonded, eliminating the need for separate adhesive application steps during the bonding process itself. The via formation is also integrated into this preliminary preparation phase.
2Adaptability or versatility
If additional manufacturing steps are added to join wafers, then vertical integration is achieved, but costs increase
Solution Approach 1:
The patent merges the adhesive material patterning, via formation, and wafer bonding into a single integrated manufacturing step. By combining these previously separate operations into one process, the patent reduces manufacturing complexity and cost while maintaining the capability for vertical integration of multiple semiconductor wafers.
3Reliability
If more manufacturing steps are used to bond wafers, then electrical interconnectivity is achieved, but the risk of defects increases
Solution Approach 1:
The patent combines via formation and wafer bonding into a single simultaneous operation. The vias are formed through the adhesive material and first substrate while the bonding occurs, eliminating separate via formation and bonding steps. This reduces the number of bonding steps while ensuring reliable electrical interconnectivity between stacked wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the reliable and cost-effective production of semiconductor devices with multiple stacked dies, providing efficient electrical interconnectivity and reducing the risk of defects, thus improving the yield and functionality of three-dimensional integrated circuit devices.
Implementation Method 1
The patterned adhesive material allows for lateral expansion of the adhesive material when the wafers are pressed together during the bonding process
Implementation Method 2
The via includes a conductive material that furnishes an electrical interconnection between the integrated circuits
Data Source
AI summary
Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.