Patterned Anodes for Copper Pillar Bump Height Control
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Solution Overview
Problem
The existing copper pillar bump fabrication process is costly and inefficient, with high processing costs and poor within-die and within-wafer uniformity due to the need for photoresist patterning and cleaning, and the inability to easily form bumps with varying heights to accommodate uneven substrate surfaces.
Innovation Solution
The use of patterned anodes in electrochemical plating allows for simpler and more cost-effective processing by eliminating the need for substrate-specific photoresist patterning and cleaning, and enables the formation of bumps with varying heights by controlling the anode pattern and plating parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photoresist patterning and cleaning is used in copper pillar bump fabrication, then bump formation can be achieved, but processing costs increase and within-die and within-wafer uniformity deteriorate
Solution Approach 1:
The patent extracts and eliminates the photoresist patterning and cleaning steps from the copper pillar bump fabrication process. Instead of using photoresist to define bump patterns, the invention directly forms bumps through electrochemical plating on exposed bond pads, removing the source of uniformity issues and processing complexity associated with photoresist manipulation
Solution Approach 2:
The bond pads themselves serve as the pattern definition through their inherent geometry and electrochemical properties. The electrochemical plating process automatically confines copper deposition to the bond pad areas through controlled potential application, eliminating the need for external photoresist patterning and allowing the substrate to define its own bump pattern
2Adaptability or versatility
If conventional electrochemical plating is used, then copper pillars can be formed, but the process cannot accommodate bumps with varying heights for uneven substrate surfaces
Solution Approach 1:
The patent introduces dynamic control of the electrochemical plating process through variable potential application. Different bond pads can be plated at different potentials or for different durations, allowing the formation of copper pillars with varying heights to accommodate uneven substrate surfaces or different electrical requirements
Solution Approach 2:
The invention applies local quality control by enabling different plating conditions for different bond pads. Each bond pad can receive customized plating parameters (potential, time, current density) to achieve the specific bump height and properties required for that location, rather than uniform plating across the entire substrate
3Productivity
If photoresist patterning is required for each substrate, then precise bump placement can be achieved, but substrate throughput decreases
Solution Approach 1:
The bond pads are pre-patterned on the substrate before the electrochemical plating step, with their geometry and spatial arrangement predetermined. This preliminary patterning eliminates the need for subsequent photoresist patterning, allowing direct plating and significantly improving substrate throughput while maintaining precise bump placement through the inherent bond pad geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing costs, improves substrate throughput, and enhances within-die and within-wafer uniformity, while allowing for the integration of bumps with different heights to accommodate varying substrate features, thus expanding the application of copper post bumps in flip-chip packaging.
Implementation Method 1
The use of patterned anodes in electrochemical plating allows for simpler and more cost-effective processing
Data Source
AI summary
This disclosure relates to a bump structure on a substrate including a copper layer, wherein the copper layer fills an opening created in a dielectric layer and a polymer layer. The bump structure further includes an under-bump-metallurgy (UBM) layer lines the opening and the copper layer is deposited over the UBM layer. The bump structure further includes a surface of the copper layer facing away from the substrate is curved. This disclosure also relates to two bump structures with different heights on a substrate where a thickness of the first bump structure is different than a thickness of the second bump structure. This disclosure also relates to a semiconductor device including a bump structure.


