Patterned Back Side Layer for Wafer Stress Counteraction

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Solution Overview

Problem

Integrated circuit wafers tend to bend, bow, and warp due to stress differences between their active and passive surfaces, which complicates handling and processing, especially after thinning, leading to precision issues during photolithography and increased fragility during dicing.

Innovation Solution

A back side layer, typically a thermoset epoxy with specific thickness and material properties, is applied to the passive side of the thinned wafer to counteract stresses, reducing bending and warping, and can be patterned to provide directional stress modulation and expose areas for dicing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the wafer is thinned to reduce overall thickness, then the wafer becomes more fragile and prone to bending and warping, but reducing thickness is necessary for certain applications and processing requirements

Engineering Contradiction:
Improvewafer thicknessVSAvoidwafer structural integrity
Core Design Contradiction:
Length of moving objectVSStrength

Solution Approach 1:

The patent applies composite materials by bonding a carrier substrate to the thinned wafer back side. The carrier substrate acts as a reinforcement layer that compensates for the loss of structural integrity caused by thinning. This composite structure allows the wafer to maintain both reduced thickness and adequate strength, resolving the contradiction between thinning and structural integrity.

Inventive Principle:
Principle #40Composite materials

2Device complexity

If the wafer is thinned before applying interconnection bumps, then processing complexity is reduced and dicing is simplified, but the wafer becomes more susceptible to bending and warping during subsequent processing steps

Engineering Contradiction:
Improveprocessing complexityVSAvoidwafer flatness
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by thinning the wafer before applying interconnection bumps and before final assembly steps. This early thinning simplifies subsequent processing and reduces overall device complexity. The carrier substrate is then added to provide the necessary structural support and flatness stability for remaining processing steps, allowing the benefits of early thinning to be realized without compromising wafer stability.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If a thick back side layer is applied to counter stress on the thinned wafer, then wafer stability and flatness are improved, but the overall device size and complexity increase

Engineering Contradiction:
Improvewafer flatnessVSAvoidstructure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent applies flexible shells and thin films by using a relatively thin carrier substrate that provides sufficient stress counteraction and flatness stability. The carrier substrate is designed with minimal necessary thickness to achieve the required mechanical support without adding excessive bulk or complexity to the overall device structure.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The back side layer effectively stabilizes the wafer, reducing bowing and warping, improving handling and processing precision, and enhancing uniformity and cost-effectiveness by allowing thinner wafers to be processed before applying bumps, thus simplifying dicing and reducing the risk of chipping.

Implementation Method 1

the back side layer may be configured to counter stress on the front side of the wafer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8643177B2Wafers including patterned back side layers thereon
Publication Date: 2014.02.04 AMKOR TECH SINGAPORE HLDG PTE LTD
  • US8643177B2 patent drawing
  • US8643177B2 patent drawing
  • US8643177B2 patent drawing

AI summary

A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the thinned wafer opposite the front side, and the back side layer may be configured to counter stress on the front side of the wafer including the plurality of integrated circuit devices thereon. After providing the back side layer, the plurality of integrated circuit devices may be separated. Related structures are also discussed.