Patterned Bonding Layer for Thinned Wafer Support and Dicing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Thinned semiconductor wafers are prone to bowing and warping during processing steps like CMP and ion implantation, and existing temporary bonding/debonding technologies are complex and costly.

Innovation Solution

A method involving a patterned bonding layer formed on the scribe line region of the device wafer, allowing a handle wafer to be bonded and then diced simultaneously, eliminating the need for redundant debonding steps and reducing processing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer thinning is performed on thinned wafers, then the semiconductor device can be fabricated, but the wafer becomes frangible and vulnerable to bowing and warping during subsequent processing steps

Engineering Contradiction:
Improvewafer thinning precisionVSAvoidwafer structural stability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A carrier wafer is introduced as an intermediary substrate to support the thinned device wafer during processing. The carrier wafer provides mechanical strength and structural stability to the fragile thinned wafer, preventing bowing and warping during subsequent steps such as CMP, etching, and ion implantation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The bonding layer is patterned into discrete regions aligned with scribe lines, separating the bonding function from the device active areas. This segmentation allows the bonding layer to be removed during dicing without affecting the device structures, enabling easy separation of the device wafer from the carrier wafer.

Inventive Principle:
Principle #1Segmentation

2Reliability

If temporary bonding/debonding technology is used to support thinned wafers, then wafer stability is improved, but the process becomes complex and costly

Engineering Contradiction:
Improvewafer structural stabilityVSAvoidprocessing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bonding layer is selectively removed by dicing along the scribe lines, extracting the bonding function only where needed for separation. This eliminates the need for a separate debonding step, simplifying the overall process while maintaining wafer stability during processing.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dicing process is merged with the bonding layer removal step. By aligning the bonding layer with the scribe lines, a single dicing operation simultaneously separates the device wafer from the carrier wafer and removes the bonding layer, reducing the number of process steps.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If a patterned bonding layer is used to bond the handle wafer, then the dicing process can remove the bonding layer simultaneously, but additional patterning steps are required

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidpatterning process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The scribe lines serve multiple functions: they define the dicing paths for separating individual devices and simultaneously define the pattern for the bonding layer. This multi-functionality eliminates the need for separate patterning steps, as the bonding layer pattern is derived from the existing scribe line geometry.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method simplifies the semiconductor device fabrication process, reduces costs, and prevents wafer damage by allowing direct separation of dices from the handle wafer without additional debonding, enhancing processing efficiency.

Implementation Method 1

performing a photo-resist development process to remove a portion of the photo-resist layer

Methodology Applied
Scientific EffectPhoto-resist development: Photography

Implementation Method 2

a handle wafer is bonded to the device wafer by the patterned bonding layer

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Implementation Method 3

the dicing process is a laser dicing process

Methodology Applied
Scientific EffectLaser dicing: Laser Ablation

Implementation Method 4

the dicing process is a saw-dicing process

Methodology Applied
Scientific EffectSaw dicing: Abrasion

Implementation Method 5

wafer thinning steps are carried out on the backside of the device wafer

Methodology Applied
Scientific EffectChemical mechanical polishing: Abrasion

Data Source

PatentUS8772136B2Method for fabricating semiconductor device
Publication Date: 2014.07.08 UNITED MICROELECTRONICS CORP
  • US8772136B2 patent drawing
  • US8772136B2 patent drawing
  • US8772136B2 patent drawing

AI summary

A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.